Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761447AbcJRNte (ORCPT ); Tue, 18 Oct 2016 09:49:34 -0400 Received: from mail-oi0-f47.google.com ([209.85.218.47]:35563 "EHLO mail-oi0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755547AbcJRNtR (ORCPT ); Tue, 18 Oct 2016 09:49:17 -0400 Date: Tue, 18 Oct 2016 08:49:15 -0500 From: Rob Herring To: Jacek Anaszewski Cc: Matt Ranostay , Tony Lindgren , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Matt Ranostay , Mark Rutland Subject: Re: [PATCH] leds: leds-pca963x: workaround group blink scaling issue Message-ID: <20161018134915.hbeiorftge56xrih@rob-hp-laptop> References: <1476364572-26849-1-git-send-email-matt@ranostay.consulting> <924a896d-b3f2-5fed-62ba-a731e79e1567@samsung.com> <20161014142047.imm4idfetphlp5od@atomide.com> <5d9476b8-b552-f745-e06d-9894fa2e542a@samsung.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5d9476b8-b552-f745-e06d-9894fa2e542a@samsung.com> User-Agent: Mutt/1.6.2-neo (2016-08-21) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2260 Lines: 53 On Mon, Oct 17, 2016 at 09:58:26AM +0200, Jacek Anaszewski wrote: > On 10/15/2016 02:00 PM, Matt Ranostay wrote: > > On Fri, Oct 14, 2016 at 7:20 AM, Tony Lindgren wrote: > > > * Jacek Anaszewski [161013 23:37]: > > > > On 10/13/2016 04:20 PM, Matt Ranostay wrote: > > > > > On Thu, Oct 13, 2016 at 4:05 PM, Jacek Anaszewski > > > > > wrote: > > > > > > Why DT property? Is it somehow dependent on the board configuration? > > > > > > How this period-scale value is calculated? Is it inferred empirically? > > > > > > > > > > > > > > > > We empirically discovered and verified this with an logic analyzer on > > > > > multiple batches of this part. > > > > > Reason for the DT entry is we aren't 100% sure that it is always going > > > > > to be the same with different board revs. > > > > > > > > > > Could be that parts clock acts differently with supply voltage. This > > > > > has been calculated by setting it an expected value, and measuring the > > > > > actual result with the logic analyzer. > > > > > > > > I'd like to have DT maintainer's ack for this. > > > > > > > > Cc Rob and Mark. > > > > > > How about do this based on the compatible property instead? If there > > > are multiple manufacturers for this part and only a certain > > > parts have this issue we should have multiple compatible properties. > > > > > > > I could only find that NXP as the manufacturer of that part. It is > > possible since the clock is internal to the chipset that the vdd of > > 2.5V is doing something undefined. > > > > > Then if it turns out all of them need this scaling there's no need > > > to update the binding. > > > > Understandable. > > Since at present we can't guarantee that all produced devices > are affected, then we should strive to avoid breaking any existing > users of the possible non-affected devices. > > In view of that the addition of a new "compatible" proposed by Tony > seems most reasonable. > > Still, DT maintainer's opinion is required. Seems like a quirk of this board, so I think the added property is fine. It could be existing users just didn't notice the rate being off. 30% is probably not all that noticeable to the human eye. Rob