Date: Thu, 20 Oct 2016 12:17:47 +0200
From: Peter Zijlstra <peterz@infradead.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Bin Gao <bin.gao@linux.intel.com>, Ingo Molnar <mingo@redhat.com>,
        "H. Peter Anvin" <hpa@zytor.com>, John Stultz <john.stultz@linaro.org>,
        x86@kernel.org, linux-kernel@vger.kernel.org, bin.gao@intel.com
Subject: Re: [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag
Message-ID: <20161020101747.GT3102@twins.programming.kicks-ass.net>
References: <20160816174240.GA33372@worksta>
 <alpine.DEB.2.20.1608241049270.5714@nanos>
 <20160825164350.GA245186@worksta>
 <alpine.DEB.2.20.1608261210090.5714@nanos>
 <alpine.DEB.2.20.1608261212080.5714@nanos>
 <20161011211121.GA15041@worksta>
 <alpine.DEB.2.20.1610120948250.5032@nanos>
 <20161013231619.GA225074@worksta>
 <alpine.DEB.2.20.1610201154020.5073@nanos>
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On Thu, Oct 20, 2016 at 11:57:03AM +0200, Thomas Gleixner wrote:
> On Thu, 13 Oct 2016, Bin Gao wrote:
> > @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
> >  		}
> >  	}
> >  
> > +	setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> > +
> > +	/*
> > +	 * For Atom SoCs TSC is the only reliable clocksource.
> > +	 * Mark TSC reliable so no watchdog on it.
> > +	 */
> > +	if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
> > +		setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> > +

AFAICT setting TSC_RELIABLE also skips the check_tsc_warp() tests in
tsc_sync.c.

This means that if someone does a Goldmont BIOS with 'features', we'll
never detect the wreckage :-/