Date: Fri, 21 Oct 2016 07:47:17 +0200
From: Peter Zijlstra <peterz@infradead.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Bin Gao <bin.gao@linux.intel.com>, Ingo Molnar <mingo@redhat.com>,
        "H. Peter Anvin" <hpa@zytor.com>, John Stultz <john.stultz@linaro.org>,
        x86@kernel.org, linux-kernel@vger.kernel.org, bin.gao@intel.com
Subject: Re: [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag
Message-ID: <20161021054717.GZ3102@twins.programming.kicks-ass.net>
References: <alpine.DEB.2.20.1608241049270.5714@nanos>
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 <alpine.DEB.2.20.1608261212080.5714@nanos>
 <20161011211121.GA15041@worksta>
 <alpine.DEB.2.20.1610120948250.5032@nanos>
 <20161013231619.GA225074@worksta>
 <alpine.DEB.2.20.1610201154020.5073@nanos>
 <20161020101747.GT3102@twins.programming.kicks-ass.net>
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On Thu, Oct 20, 2016 at 09:37:50PM +0200, Thomas Gleixner wrote:

> Well, we have the same issue on other platforms/models which set the
> reliable flag.

I was not aware we had other platforms doing this, git grep tells me
intel-mid does this as well..

> So one sanity check we can do is to read the IA32_TSC_ADJUST MSR on all
> cores. They should all have the same value (usually 0) or at least have a
> very minimal delta. If that's off by more than 1us then something is fishy
> especially on single socket systems. We could at least WARN about it.
> 
> We could do this in idle occasionally as well, so we can detect the dreaded
> "SMI wants to hide the cycles" crapola.

Indeed, that sounds like the best we can; and probably should; do.