Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934172AbcJUOM2 (ORCPT ); Fri, 21 Oct 2016 10:12:28 -0400 Received: from mail-qk0-f181.google.com ([209.85.220.181]:36045 "EHLO mail-qk0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933287AbcJUOMV (ORCPT ); Fri, 21 Oct 2016 10:12:21 -0400 Date: Fri, 21 Oct 2016 16:12:17 +0200 From: Daniel Lezcano To: Noam Camus Cc: robh+dt@kernel.org, mark.rutland@arm.com, tglx@linutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/3] ARC: [plat-eznps] remove macros for timer0 TSI Message-ID: <20161021141217.GA5553@mai> References: <1476370350-3853-1-git-send-email-noamca@mellanox.com> <1476370350-3853-3-git-send-email-noamca@mellanox.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1476370350-3853-3-git-send-email-noamca@mellanox.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1194 Lines: 34 On Thu, Oct 13, 2016 at 05:52:29PM +0300, Noam Camus wrote: > From: Noam Camus > > Now it is defined at include/soc/nps/mtm.h > It will be used by module from driver/clocksource/ > This patch should be folded with the previous one in order to prevent to break the git bisecting, otherwise there will be duplicate macros at some point, leading to a compilation failure. > Signed-off-by: Noam Camus > --- > arch/arc/plat-eznps/include/plat/ctop.h | 2 -- > 1 files changed, 0 insertions(+), 2 deletions(-) > > diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h > index 9d6718c..ee2e32d 100644 > --- a/arch/arc/plat-eznps/include/plat/ctop.h > +++ b/arch/arc/plat-eznps/include/plat/ctop.h > @@ -46,9 +46,7 @@ > #define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300) > > /* EZchip core instructions */ > -#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF > #define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF > -#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3 > #define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103 > #define CTOP_INST_SCHD_RW 0x3E6F7004 > #define CTOP_INST_SCHD_RD 0x3E6F7084 > -- > 1.7.1 >