Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936514AbcJVJ2x (ORCPT ); Sat, 22 Oct 2016 05:28:53 -0400 Received: from slow1-d.mail.gandi.net ([217.70.178.86]:55446 "EHLO slow1-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935727AbcJVJ2v (ORCPT ); Sat, 22 Oct 2016 05:28:51 -0400 X-Originating-IP: 1.129.33.158 Subject: Re: [PATCH] drm/amd/powerplay: mark symbols static where possible To: Baoyou Xie , alexander.deucher@amd.com, airlied@linux.ie, Rex.Zhu@amd.com, Jammy.Zhou@amd.com, JinHuiEric.Huang@amd.com, tom.stdenis@amd.com, vitaly.prosyak@amd.com, eric.yang2@amd.com, Young.Yang@amd.com, ray.huang@amd.com, arnd@arndb.de, dan.carpenter@oracle.com, Flora.Cui@amd.com, nils.wallmenius@gmail.com, Monk.Liu@amd.com, Qingqing.Wang@amd.com, Frank.Min@amd.com References: <1477126582-2906-1-git-send-email-baoyou.xie@linaro.org> Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, xie.baoyou@zte.com.cn, han.fei@zte.com.cn, tang.qiang007@zte.com.cn From: "Edward O'Callaghan" Message-ID: Date: Sat, 22 Oct 2016 20:28:24 +1100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <1477126582-2906-1-git-send-email-baoyou.xie@linaro.org> Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="ahoPK7JB5jtoclTFVDrMcUPScpldrm1Mo" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 23451 Lines: 649 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --ahoPK7JB5jtoclTFVDrMcUPScpldrm1Mo Content-Type: multipart/mixed; boundary="E9adAe49pmOdMlqThKlRamwIOWJRMbFxf"; protected-headers="v1" From: Edward O'Callaghan To: Baoyou Xie , alexander.deucher@amd.com, airlied@linux.ie, Rex.Zhu@amd.com, Jammy.Zhou@amd.com, JinHuiEric.Huang@amd.com, tom.stdenis@amd.com, vitaly.prosyak@amd.com, eric.yang2@amd.com, Young.Yang@amd.com, ray.huang@amd.com, arnd@arndb.de, dan.carpenter@oracle.com, Flora.Cui@amd.com, nils.wallmenius@gmail.com, Monk.Liu@amd.com, Qingqing.Wang@amd.com, Frank.Min@amd.com Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, xie.baoyou@zte.com.cn, han.fei@zte.com.cn, tang.qiang007@zte.com.cn Message-ID: Subject: Re: [PATCH] drm/amd/powerplay: mark symbols static where possible References: <1477126582-2906-1-git-send-email-baoyou.xie@linaro.org> In-Reply-To: <1477126582-2906-1-git-send-email-baoyou.xie@linaro.org> --E9adAe49pmOdMlqThKlRamwIOWJRMbFxf Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Oh dear, still more of these? Why not perhaps fix them all at once into a series? In any case, Acked-by: Edward O'Callaghan On 10/22/2016 07:56 PM, Baoyou Xie wrote: > We get a few warnings when building kernel with W=3D1: > drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/fiji_smumgr.c:162:5: war= ning: no previous prototype for 'fiji_setup_pwr_virus' [-Wmissing-prototy= pes] > drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/fiji_smc.c:2052:5: warni= ng: no previous prototype for 'fiji_program_mem_timing_parameters' [-Wmis= sing-prototypes] > drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/polaris10_smumgr.c:175:5= : warning: no previous prototype for 'polaris10_avfs_event_mgr' [-Wmissin= g-prototypes] > drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_hwmgr.c:1020:5: warnin= g: no previous prototype for 'cz_tf_reset_acp_boot_level' [-Wmissing-prot= otypes] > drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:92:26: warni= ng: no previous prototype for 'cast_phw_smu7_power_state' [-Wmissing-prot= otypes] > .... >=20 > In fact, these functions are only used in the file in which they are > declared and don't need a declaration, but can be made static. > So this patch marks these functions with 'static'. >=20 > Signed-off-by: Baoyou Xie > --- > drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 6 ++- > drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 12 +++--- > .../amd/powerplay/hwmgr/process_pptables_v1_0.c | 6 +-- > .../gpu/drm/amd/powerplay/hwmgr/processpptables.c | 4 +- > .../amd/powerplay/hwmgr/smu7_clockpowergating.c | 10 ++--- > drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 49 ++++++++++++--= -------- > drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c | 2 +- > drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 12 +++--- > .../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 5 ++- > 9 files changed, 57 insertions(+), 49 deletions(-) >=20 > diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gp= u/drm/amd/powerplay/amd_powerplay.c > index 7174f7a..eecfbc5 100644 > --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > @@ -436,7 +436,9 @@ static enum PP_StateUILabel power_state_convert(enu= m amd_pm_state_type state) > } > } > =20 > -int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, vo= id *input, void *output) > +static int > +pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *= input, > + void *output) > { > int ret =3D 0; > struct pp_instance *pp_handle; > @@ -475,7 +477,7 @@ int pp_dpm_dispatch_tasks(void *handle, enum amd_pp= _event event_id, void *input, > return ret; > } > =20 > -enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) > +static enum amd_pm_state_type pp_dpm_get_current_power_state(void *han= dle) > { > struct pp_hwmgr *hwmgr; > struct pp_power_state *state; > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/g= pu/drm/amd/powerplay/hwmgr/cz_hwmgr.c > index 9604249..4b14f25 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c > @@ -66,7 +66,7 @@ static const struct cz_power_state *cast_const_PhwCzP= owerState( > return (struct cz_power_state *)hw_ps; > } > =20 > -uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr, > +static uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr, > uint32_t clock, uint32_t msg) > { > int i =3D 0; > @@ -1017,7 +1017,7 @@ static int cz_tf_program_bootup_state(struct pp_h= wmgr *hwmgr, void *input, > return 0; > } > =20 > -int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input, > +static int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *in= put, > void *output, void *storage, int result) > { > struct cz_hwmgr *cz_hwmgr =3D (struct cz_hwmgr *)(hwmgr->backend); > @@ -1225,7 +1225,7 @@ static int cz_hwmgr_backend_fini(struct pp_hwmgr = *hwmgr) > return 0; > } > =20 > -int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) > +static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) > { > struct cz_hwmgr *cz_hwmgr =3D (struct cz_hwmgr *)(hwmgr->backend); > =20 > @@ -1239,7 +1239,7 @@ int cz_phm_force_dpm_highest(struct pp_hwmgr *hwm= gr) > return 0; > } > =20 > -int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) > +static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) > { > struct cz_hwmgr *cz_hwmgr =3D (struct cz_hwmgr *)(hwmgr->backend); > struct phm_clock_voltage_dependency_table *table =3D > @@ -1277,7 +1277,7 @@ int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hw= mgr) > return 0; > } > =20 > -int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) > +static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) > { > struct cz_hwmgr *cz_hwmgr =3D (struct cz_hwmgr *)(hwmgr->backend); > =20 > @@ -1533,7 +1533,7 @@ static int cz_dpm_get_pp_table_entry(struct pp_hw= mgr *hwmgr, > return result; > } > =20 > -int cz_get_power_state_size(struct pp_hwmgr *hwmgr) > +static int cz_get_power_state_size(struct pp_hwmgr *hwmgr) > { > return sizeof(struct cz_power_state); > } > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.= c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c > index 7de701d..155cd0d 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c > @@ -131,7 +131,7 @@ static int set_platform_caps(struct pp_hwmgr *hwmgr= , uint32_t powerplay_caps) > /** > * Private Function to get the PowerPlay Table Address. > */ > -const void *get_powerplay_table(struct pp_hwmgr *hwmgr) > +static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) > { > int index =3D GetIndexIntoMasterTable(DATA, PowerPlayInfo); > =20 > @@ -1049,7 +1049,7 @@ static int check_powerplay_tables( > return 0; > } > =20 > -int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr) > +static int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr) > { > int result =3D 0; > const ATOM_Tonga_POWERPLAYTABLE *powerplay_table; > @@ -1100,7 +1100,7 @@ int pp_tables_v1_0_initialize(struct pp_hwmgr *hw= mgr) > return result; > } > =20 > -int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr) > +static int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr) > { > struct phm_ppt_v1_information *pp_table_information =3D > (struct phm_ppt_v1_information *)(hwmgr->pptable); > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/dr= ivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c > index ccf7ebe..bd1f190 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c > @@ -1507,7 +1507,7 @@ static int init_phase_shedding_table(struct pp_hw= mgr *hwmgr, > return 0; > } > =20 > -int get_number_of_vce_state_table_entries( > +static int get_number_of_vce_state_table_entries( > struct pp_hwmgr *hwmgr) > { > const ATOM_PPLIB_POWERPLAYTABLE *table =3D > @@ -1521,7 +1521,7 @@ int get_number_of_vce_state_table_entries( > return 0; > } > =20 > -int get_vce_state_table_entry(struct pp_hwmgr *hwmgr, > +static int get_vce_state_table_entry(struct pp_hwmgr *hwmgr, > unsigned long i, > struct pp_vce_state *vce_state, > void **clock_info, > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.= c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c > index 6eb6db1..f5a58d4 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c > @@ -75,7 +75,7 @@ int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr) > return 0; > } > =20 > -int smu7_powerup_uvd(struct pp_hwmgr *hwmgr) > +static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr) > { > if (phm_cf_want_uvd_power_gating(hwmgr)) { > if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > @@ -91,7 +91,7 @@ int smu7_powerup_uvd(struct pp_hwmgr *hwmgr) > return 0; > } > =20 > -int smu7_powerdown_vce(struct pp_hwmgr *hwmgr) > +static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr) > { > if (phm_cf_want_vce_power_gating(hwmgr)) > return smum_send_msg_to_smc(hwmgr->smumgr, > @@ -99,7 +99,7 @@ int smu7_powerdown_vce(struct pp_hwmgr *hwmgr) > return 0; > } > =20 > -int smu7_powerup_vce(struct pp_hwmgr *hwmgr) > +static int smu7_powerup_vce(struct pp_hwmgr *hwmgr) > { > if (phm_cf_want_vce_power_gating(hwmgr)) > return smum_send_msg_to_smc(hwmgr->smumgr, > @@ -107,7 +107,7 @@ int smu7_powerup_vce(struct pp_hwmgr *hwmgr) > return 0; > } > =20 > -int smu7_powerdown_samu(struct pp_hwmgr *hwmgr) > +static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr) > { > if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_SamuPowerGating)) > @@ -116,7 +116,7 @@ int smu7_powerdown_samu(struct pp_hwmgr *hwmgr) > return 0; > } > =20 > -int smu7_powerup_samu(struct pp_hwmgr *hwmgr) > +static int smu7_powerup_samu(struct pp_hwmgr *hwmgr) > { > if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_SamuPowerGating)) > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers= /gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > index 609996c..33b7528 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > @@ -89,7 +89,7 @@ enum DPM_EVENT_SRC { > =20 > static const unsigned long PhwVIslands_Magic =3D (unsigned long)(PHM_V= Islands_Magic); > =20 > -struct smu7_power_state *cast_phw_smu7_power_state( > +static struct smu7_power_state *cast_phw_smu7_power_state( > struct pp_hw_power_state *hw_ps) > { > PP_ASSERT_WITH_CODE((PhwVIslands_Magic =3D=3D hw_ps->magic), > @@ -99,7 +99,7 @@ struct smu7_power_state *cast_phw_smu7_power_state( > return (struct smu7_power_state *)hw_ps; > } > =20 > -const struct smu7_power_state *cast_const_phw_smu7_power_state( > +static const struct smu7_power_state *cast_const_phw_smu7_power_state(= > const struct pp_hw_power_state *hw_ps) > { > PP_ASSERT_WITH_CODE((PhwVIslands_Magic =3D=3D hw_ps->magic), > @@ -115,7 +115,7 @@ const struct smu7_power_state *cast_const_phw_smu7_= power_state( > * @param hwmgr the address of the powerplay hardware manager. > * @return always 0 > */ > -int smu7_get_mc_microcode_version (struct pp_hwmgr *hwmgr) > +static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr) > { > cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); > =20 > @@ -124,7 +124,7 @@ int smu7_get_mc_microcode_version (struct pp_hwmgr = *hwmgr) > return 0; > } > =20 > -uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr) > +static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr) > { > uint32_t speedCntl =3D 0; > =20 > @@ -135,7 +135,7 @@ uint16_t smu7_get_current_pcie_speed(struct pp_hwmg= r *hwmgr) > PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); > } > =20 > -int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) > +static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) > { > uint32_t link_width; > =20 > @@ -155,7 +155,7 @@ int smu7_get_current_pcie_lane_number(struct pp_hwm= gr *hwmgr) > * @param pHwMgr the address of the powerplay hardware manager. > * @return always PP_Result_OK > */ > -int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) > +static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) > { > if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK) > smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable); > @@ -802,7 +802,7 @@ static int smu7_setup_dpm_tables_v1(struct pp_hwmgr= *hwmgr) > return 0; > } > =20 > -int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) > +static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) > { > struct smu7_hwmgr *data =3D (struct smu7_hwmgr *)(hwmgr->backend); > =20 > @@ -1153,7 +1153,7 @@ static int smu7_disable_thermal_auto_throttle(str= uct pp_hwmgr *hwmgr) > return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSourc= e_Thermal); > } > =20 > -int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr) > +static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr) > { > struct smu7_hwmgr *data =3D (struct smu7_hwmgr *)(hwmgr->backend); > data->pcie_performance_request =3D true; > @@ -1161,7 +1161,7 @@ int smu7_pcie_performance_request(struct pp_hwmgr= *hwmgr) > return 0; > } > =20 > -int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) > +static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) > { > int tmp_result =3D 0; > int result =3D 0; > @@ -1277,7 +1277,7 @@ int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)= > return 0; > } > =20 > -int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr) > +static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr) > { > int tmp_result, result =3D 0; > =20 > @@ -1341,7 +1341,7 @@ int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr= ) > return result; > } > =20 > -int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr) > +static int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr) > { > =20 > return 0; > @@ -1864,7 +1864,7 @@ static int smu7_set_private_data_based_on_pptable= _v1(struct pp_hwmgr *hwmgr) > return 0; > } > =20 > -int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr) > +static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr) > { > struct phm_ppt_v1_information *table_info =3D > (struct phm_ppt_v1_information *)(hwmgr->pptable); > @@ -2253,7 +2253,7 @@ static int smu7_set_private_data_based_on_pptable= _v0(struct pp_hwmgr *hwmgr) > return 0; > } > =20 > -int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) > +static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) > { > struct smu7_hwmgr *data; > int result; > @@ -3672,14 +3672,16 @@ static int smu7_set_max_fan_pwm_output(struct p= p_hwmgr *hwmgr, uint16_t us_max_f > PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm); > } > =20 > -int smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_di= splay) > +static int > +smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_displa= y) > { > PPSMC_Msg msg =3D has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_= Msg)PPSMC_NoDisplay; > =20 > return (smum_send_msg_to_smc(hwmgr->smumgr, msg) =3D=3D 0) ? 0 : -1;= > } > =20 > -int smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr= *hwmgr) > +static int > +smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hw= mgr) > { > uint32_t num_active_displays =3D 0; > struct cgs_display_info info =3D {0}; > @@ -3701,7 +3703,7 @@ int smu7_notify_smc_display_config_after_ps_adjus= tment(struct pp_hwmgr *hwmgr) > * @param hwmgr the address of the powerplay hardware manager. > * @return always OK > */ > -int smu7_program_display_gap(struct pp_hwmgr *hwmgr) > +static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) > { > struct smu7_hwmgr *data =3D (struct smu7_hwmgr *)(hwmgr->backend); > uint32_t num_active_displays =3D 0; > @@ -3751,7 +3753,7 @@ int smu7_program_display_gap(struct pp_hwmgr *hwm= gr) > return 0; > } > =20 > -int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr) > +static int smu7_display_configuration_changed_task(struct pp_hwmgr *hw= mgr) > { > return smu7_program_display_gap(hwmgr); > } > @@ -3775,13 +3777,14 @@ static int smu7_set_max_fan_rpm_output(struct p= p_hwmgr *hwmgr, uint16_t us_max_f > PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm); > } > =20 > -int smu7_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, > +static int smu7_register_internal_thermal_interrupt(struct pp_hwmgr *h= wmgr, > const void *thermal_interrupt_info) > { > return 0; > } > =20 > -bool smu7_check_smc_update_required_for_display_configuration(struct p= p_hwmgr *hwmgr) > +static bool smu7_check_smc_update_required_for_display_configuration( > + struct pp_hwmgr *hwmgr) > { > struct smu7_hwmgr *data =3D (struct smu7_hwmgr *)(hwmgr->backend); > bool is_update_required =3D false; > @@ -3810,7 +3813,9 @@ static inline bool smu7_are_power_levels_equal(co= nst struct smu7_performance_lev > (pl1->pcie_lane =3D=3D pl2->pcie_lane)); > } > =20 > -int smu7_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw= _power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equ= al) > +static int smu7_check_states_equal(struct pp_hwmgr *hwmgr, > + const struct pp_hw_power_state *pstate1, > + const struct pp_hw_power_state *pstate2, bool *equal) > { > const struct smu7_power_state *psa; > const struct smu7_power_state *psb; > @@ -3843,7 +3848,7 @@ int smu7_check_states_equal(struct pp_hwmgr *hwmg= r, const struct pp_hw_power_sta > return 0; > } > =20 > -int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr) > +static int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr) > { > struct smu7_hwmgr *data =3D (struct smu7_hwmgr *)(hwmgr->backend); > =20 > @@ -3972,7 +3977,7 @@ static int smu7_init_sclk_threshold(struct pp_hwm= gr *hwmgr) > return 0; > } > =20 > -int smu7_setup_asic_task(struct pp_hwmgr *hwmgr) > +static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr) > { > int tmp_result, result =3D 0; > =20 > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/= gpu/drm/amd/powerplay/smumgr/fiji_smc.c > index 76310ac..e7e8944 100644 > --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c > @@ -2049,7 +2049,7 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr = *hwmgr) > return 0; > } > =20 > -int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) > +static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) > { > struct smu7_hwmgr *data =3D (struct smu7_hwmgr *)(hwmgr->backend); > =20 > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drive= rs/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c > index 02fe1df..b86e48f 100755 > --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c > @@ -159,7 +159,7 @@ static int fiji_start_smu_in_non_protection_mode(st= ruct pp_smumgr *smumgr) > return result; > } > =20 > -int fiji_setup_pwr_virus(struct pp_smumgr *smumgr) > +static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr) > { > int i, result =3D -1; > uint32_t reg, data; > @@ -224,7 +224,7 @@ static int fiji_start_avfs_btc(struct pp_smumgr *sm= umgr) > return result; > } > =20 > -int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr) > +static int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr) > { > int result =3D 0; > uint32_t table_start; > @@ -260,7 +260,7 @@ int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *s= mumgr) > return result; > } > =20 > -int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr) > +static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumg= r) > { > int32_t vr_config; > uint32_t table_start; > @@ -299,7 +299,7 @@ int fiji_setup_graphics_level_structure(struct pp_s= mumgr *smumgr) > } > =20 > /* Work in Progress */ > -int fiji_restore_vft_table(struct pp_smumgr *smumgr) > +static int fiji_restore_vft_table(struct pp_smumgr *smumgr) > { > struct fiji_smumgr *priv =3D (struct fiji_smumgr *)(smumgr->backend);= > =20 > @@ -311,7 +311,7 @@ int fiji_restore_vft_table(struct pp_smumgr *smumgr= ) > } > =20 > /* Work in Progress */ > -int fiji_save_vft_table(struct pp_smumgr *smumgr) > +static int fiji_save_vft_table(struct pp_smumgr *smumgr) > { > struct fiji_smumgr *priv =3D (struct fiji_smumgr *)(smumgr->backend);= > =20 > @@ -322,7 +322,7 @@ int fiji_save_vft_table(struct pp_smumgr *smumgr) > return -EINVAL; > } > =20 > -int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started) > +static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_star= ted) > { > struct fiji_smumgr *priv =3D (struct fiji_smumgr *)(smumgr->backend);= > =20 > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/= drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c > index 5c3598a..f38a687 100644 > --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c > @@ -118,7 +118,7 @@ static int polaris10_perform_btc(struct pp_smumgr *= smumgr) > } > =20 > =20 > -int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)= > +static int polaris10_setup_graphics_level_structure(struct pp_smumgr *= smumgr) > { > uint32_t vr_config; > uint32_t dpm_table_start; > @@ -172,7 +172,8 @@ int polaris10_setup_graphics_level_structure(struct= pp_smumgr *smumgr) > return 0; > } > =20 > -int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_IN= TACT) > +static int > +polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT= ) > { > struct polaris10_smumgr *smu_data =3D (struct polaris10_smumgr *)(smu= mgr->backend); > =20 >=20 --E9adAe49pmOdMlqThKlRamwIOWJRMbFxf-- --ahoPK7JB5jtoclTFVDrMcUPScpldrm1Mo Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJYCzE4AAoJEP4bvbfZuWjbJC4P/3joUqGiUVVfsZiCqyurHJt9 Qey5oUCA9n5Mkbb6uYo25wGe8fVebTiEUl2oTIubrGZOufq3qX4CY3W9gTZoqr7O BYGU4X+rUlf0e57pWOTL9Lf1TxP/uiLKNPjUzMq89ddHuqJtVdD+VMzV95VmKxfd 3cFi22azN94xntlg+dVS0y9cbiyhB0C3oglHlBhJVN4/uBHqzb1vtUDGhFfkAVBM UEVih9hpZCv1lFhazm54w/Z7JlcZSJjkvBQbAM+cMU33u5mKRamzVMQqijcS+PeV s5zYIZ0vD1vlsHGyXF+5XognfU0loWVBqihSwn6Id8UZA+TLwb5AhV6BVMM+q5as dmlKyPufYppSFSrUmr5kK/Y5fjuBn3u3lP4dqFi1Er8WGi5yG8HZP9BAIOs2n9DH bYq5PkbeHgbLmQBqT//bN5Gyf0yHuacQf7vSqPkiI/eyZ/YPRhpjpnCY+RnkEOOl nMQI7ek6/EVG/KLi9Vl4jG4roGdxoPR4Dlyw/qPLNs5zt5LFkPYYmbzIHPwKD1Oq 8SNCkMpKeoc7PSz/vVRRPDWa9VAts2vKxl7mjMfUUrCQADQQI0Tb5a85W5PqYQa/ n/oKNnxyHfza0ojRY9O/8jaPurPBFQ1xdcA5INQvjRNBlgZci37vZLTJm1yxe5/u F/pJDtjmvJ9hTUL4oPH9 =t/n0 -----END PGP SIGNATURE----- --ahoPK7JB5jtoclTFVDrMcUPScpldrm1Mo--