Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756199AbcJVWjm (ORCPT ); Sat, 22 Oct 2016 18:39:42 -0400 Received: from mail-out.m-online.net ([212.18.0.9]:55972 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756125AbcJVWjl (ORCPT ); Sat, 22 Oct 2016 18:39:41 -0400 X-Auth-Info: eG0dHxcrld0SHs3767IVFnVesXMiBF3jEuqCr2jrGRg= Subject: Re: [PATCH v2 0/9] mtd: spi-nor: parse SFDP tables to setup (Q)SPI memories To: Jagan Teki , Cyrille Pitchen References: Cc: Brian Norris , "linux-mtd@lists.infradead.org" , nicolas.ferre@atmel.com, boris.brezillon@free-electrons.com, "linux-kernel@vger.kernel.org" From: Marek Vasut Message-ID: Date: Sat, 22 Oct 2016 22:33:29 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Icedove/45.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1302 Lines: 30 On 10/22/2016 01:00 PM, Jagan Teki wrote: > On Wed, Oct 5, 2016 at 5:30 PM, Cyrille Pitchen > wrote: >> Hi all, >> >> This series extends support of SPI protocols to new protocols such as >> SPI x-2-2 and SPI x-4-4. Also spi_nor_scan() tries now to select the right >> op codes, timing parameters (number of mode and dummy cycles) and erase >> sector size by parsing the Serial Flash Discoverable Parameter (SFDP) >> tables, when available, as defined in the JEDEC JESD216 specifications. >> >> When SFDP tables are not available, legacy settings are still used for >> backward compatibility (SPI and earlier QSPI memories). >> >> Support of SPI memories >128Mbits is also improved by using the 4byte >> address instruction set, when available. Using those dedicated op codes >> is stateless as opposed to enter the 4byte address mode, hence a better >> compatibility with some boot loaders which expect to use 3byte address >> op codes. > > The memories which are > 128Mbits should have 4-bytes addressing > support based on my experience, do you think BAR is also required > atleast from spi-nor side? Yes, I believe BAR is still required for broken/dumb flash chips. Not all chips > 16 MiB support dedicated 4-byte addressing opcodes :-( -- Best regards, Marek Vasut