Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934216AbcJXHli (ORCPT ); Mon, 24 Oct 2016 03:41:38 -0400 Received: from s159.web-hosting.com ([68.65.120.118]:45139 "EHLO s159.web-hosting.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932233AbcJXHlg (ORCPT ); Mon, 24 Oct 2016 03:41:36 -0400 MIME-Version: 1.0 In-Reply-To: References: From: Jagan Teki Date: Mon, 24 Oct 2016 13:11:29 +0530 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 0/9] mtd: spi-nor: parse SFDP tables to setup (Q)SPI memories To: Marek Vasut Cc: Cyrille Pitchen , Brian Norris , "linux-mtd@lists.infradead.org" , nicolas.ferre@atmel.com, boris.brezillon@free-electrons.com, "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 X-OutGoing-Spam-Status: No, score=-2.9 X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server159.web-hosting.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - openedev.com X-Get-Message-Sender-Via: server159.web-hosting.com: authenticated_id: jagan@openedev.com X-Authenticated-Sender: server159.web-hosting.com: jagan@openedev.com X-Source: X-Source-Args: X-Source-Dir: X-From-Rewrite: unmodified, already matched Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1719 Lines: 39 On Sun, Oct 23, 2016 at 2:03 AM, Marek Vasut wrote: > On 10/22/2016 01:00 PM, Jagan Teki wrote: >> On Wed, Oct 5, 2016 at 5:30 PM, Cyrille Pitchen >> wrote: >>> Hi all, >>> >>> This series extends support of SPI protocols to new protocols such as >>> SPI x-2-2 and SPI x-4-4. Also spi_nor_scan() tries now to select the right >>> op codes, timing parameters (number of mode and dummy cycles) and erase >>> sector size by parsing the Serial Flash Discoverable Parameter (SFDP) >>> tables, when available, as defined in the JEDEC JESD216 specifications. >>> >>> When SFDP tables are not available, legacy settings are still used for >>> backward compatibility (SPI and earlier QSPI memories). >>> >>> Support of SPI memories >128Mbits is also improved by using the 4byte >>> address instruction set, when available. Using those dedicated op codes >>> is stateless as opposed to enter the 4byte address mode, hence a better >>> compatibility with some boot loaders which expect to use 3byte address >>> op codes. >> >> The memories which are > 128Mbits should have 4-bytes addressing >> support based on my experience, do you think BAR is also required >> atleast from spi-nor side? > > Yes, I believe BAR is still required for broken/dumb flash chips. > Not all chips > 16 MiB support dedicated 4-byte addressing opcodes :-( Do you have list for those broken chips? because I never find any chips which has > 16 MiB with not support of 4-byte address opcodes and I've seen the controller has dependable with BAR though it can access > 16MiB ex: zynq qspi/ thanks! -- Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India.