Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757085AbcJXKTD (ORCPT ); Mon, 24 Oct 2016 06:19:03 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:44422 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756524AbcJXKS6 (ORCPT ); Mon, 24 Oct 2016 06:18:58 -0400 DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org C5D5361B11 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=sricharan@codeaurora.org From: Sricharan R To: sboyd@codeaurora.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, rnayak@codeaurora.org, stanimir.varbanov@linaro.org Cc: sricharan@codeaurora.org Subject: [PATCH 1/3] clk: qcom: gdsc: Add support for gdscs with HW control Date: Mon, 24 Oct 2016 15:48:15 +0530 Message-Id: <1477304297-5248-2-git-send-email-sricharan@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1477304297-5248-1-git-send-email-sricharan@codeaurora.org> References: <1477304297-5248-1-git-send-email-sricharan@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2144 Lines: 69 From: Rajendra Nayak Some GDSCs might support a HW control mode, where in the power domain (gdsc) is brought in and out of low power state (while unsued) without any SW assistance, saving power. Such GDSCs can be configured in a HW control mode when powered on until they are explicitly requested to be powered off by software. Signed-off-by: Rajendra Nayak Signed-off-by: Sricharan R --- drivers/clk/qcom/gdsc.c | 15 +++++++++++++++ drivers/clk/qcom/gdsc.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index f12d7b2..a5e1c8c 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -55,6 +55,13 @@ static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg) return !!(val & PWR_ON_MASK); } +static int gdsc_hwctrl(struct gdsc *sc, bool en) +{ + u32 val = en ? HW_CONTROL_MASK : 0; + + return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val); +} + static int gdsc_toggle_logic(struct gdsc *sc, bool en) { int ret; @@ -164,6 +171,10 @@ static int gdsc_enable(struct generic_pm_domain *domain) */ udelay(1); + /* Turn on HW trigger mode if supported */ + if (sc->flags & HW_CTRL) + gdsc_hwctrl(sc, true); + return 0; } @@ -174,6 +185,10 @@ static int gdsc_disable(struct generic_pm_domain *domain) if (sc->pwrsts == PWRSTS_ON) return gdsc_assert_reset(sc); + /* Turn off HW trigger mode if supported */ + if (sc->flags & HW_CTRL) + gdsc_hwctrl(sc, false); + if (sc->pwrsts & PWRSTS_OFF) gdsc_clear_mem_on(sc); diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 3bf497c..b1f30f8 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -50,6 +50,7 @@ struct gdsc { #define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) const u8 flags; #define VOTABLE BIT(0) +#define HW_CTRL BIT(1) struct reset_controller_dev *rcdev; unsigned int *resets; unsigned int reset_count; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation