Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757325AbcJXKTR (ORCPT ); Mon, 24 Oct 2016 06:19:17 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:44547 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757258AbcJXKTO (ORCPT ); Mon, 24 Oct 2016 06:19:14 -0400 DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org A54D161B2C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=sricharan@codeaurora.org From: Sricharan R To: sboyd@codeaurora.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, rnayak@codeaurora.org, stanimir.varbanov@linaro.org Cc: sricharan@codeaurora.org Subject: [PATCH 3/3] clk: qcom: Set BRANCH_HALT_DELAY flags for venus core0/1 clks Date: Mon, 24 Oct 2016 15:48:17 +0530 Message-Id: <1477304297-5248-4-git-send-email-sricharan@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1477304297-5248-1-git-send-email-sricharan@codeaurora.org> References: <1477304297-5248-1-git-send-email-sricharan@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1135 Lines: 34 With the venus subcore0/1 gdscs(powerdomains) in hw controlled mode, the clock controller does not handle the status bit for the clocks in that domain. So avoid checking for the status bit of those clocks by setting the BRANCH_HALT_DELAY flag. This avoids the WARN_ONs which otherwise occurs when enabling/disabling those clocks. Signed-off-by: Sricharan R --- drivers/clk/qcom/mmcc-msm8996.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index 41aabe3..8f3f480 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c @@ -1760,6 +1760,7 @@ enum { }; static struct clk_branch video_subcore0_clk = { + .halt_check = BRANCH_HALT_DELAY, .halt_reg = 0x1048, .clkr = { .enable_reg = 0x1048, @@ -1775,6 +1776,7 @@ enum { }; static struct clk_branch video_subcore1_clk = { + .halt_check = BRANCH_HALT_DELAY, .halt_reg = 0x104c, .clkr = { .enable_reg = 0x104c, -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation