Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755018AbcJYUXv (ORCPT ); Tue, 25 Oct 2016 16:23:51 -0400 Received: from mail-pf0-f179.google.com ([209.85.192.179]:33849 "EHLO mail-pf0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752707AbcJYUXs (ORCPT ); Tue, 25 Oct 2016 16:23:48 -0400 From: Kevin Hilman To: Bartosz Golaszewski Cc: Michael Turquette , Sekhar Nori , Rob Herring , Frank Rowand , Mark Rutland , Peter Ujfalusi , Russell King , LKML , arm-soc , linux-drm , linux-devicetree , Jyri Sarha , Tomi Valkeinen , David Airlie , Laurent Pinchart Subject: Re: [RFC v2] ARM: memory: da8xx-ddrctl: new driver Organization: BayLibre References: <1477402876-22472-1-git-send-email-bgolaszewski@baylibre.com> <1477402876-22472-2-git-send-email-bgolaszewski@baylibre.com> <7hy41ctipa.fsf@baylibre.com> Date: Tue, 25 Oct 2016 13:23:46 -0700 In-Reply-To: <7hy41ctipa.fsf@baylibre.com> (Kevin Hilman's message of "Tue, 25 Oct 2016 10:57:37 -0700") Message-ID: <7hoa28tbxp.fsf@baylibre.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.5 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2460 Lines: 60 Kevin Hilman writes: > Bartosz Golaszewski writes: > >> Create a new driver for the da8xx DDR2/mDDR controller and implement >> support for writing to the Peripheral Bus Burst Priority Register. >> >> Signed-off-by: Bartosz Golaszewski >> --- >> .../memory-controllers/ti-da8xx-ddrctl.txt | 20 +++ >> drivers/memory/Kconfig | 8 + >> drivers/memory/Makefile | 1 + >> drivers/memory/da8xx-ddrctl.c | 175 +++++++++++++++++++++ >> 4 files changed, 204 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt >> create mode 100644 drivers/memory/da8xx-ddrctl.c >> >> diff --git >> a/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt >> b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt >> new file mode 100644 >> index 0000000..7e271dd >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt >> @@ -0,0 +1,20 @@ >> +* Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory controller >> + >> +The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs features >> +a set of registers which allow to tweak the controller's behavior. >> + >> +Documentation: >> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf >> + >> +Required properties: >> + >> +- compatible: "ti,da850-ddr-controller" - for da850 SoC based boards >> +- reg: a tuple containing the base address of the memory >> + controller and the size of the memory area to map >> + >> +Example for da850 shown below. >> + >> +ddrctl { >> + compatible = "ti,da850-ddr-controller"; >> + reg = <0xB0000000 0x100>; >> +}; > > Axel's series for the USB PHY reminded me that the PHY also has some > config registers in this same area, and his series creates a syscon for > a similar range of registers. > > Could you create a syscon for the SYSCFG0 registers, which would then > be used by ths driver and your other drivers/bus driver? Then the > binding would just reference the sysconf via phandle, and your driver > can use syscon_regmap_lookup_by_phandle() Nevermind. I though that the config register in this driver was also in SYSCFG0, but I see now that it's in the reg region of the DDR controller itself, so no syscon is needed. Kevin