Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751128AbcJZENC (ORCPT ); Wed, 26 Oct 2016 00:13:02 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:33214 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750730AbcJZEM7 (ORCPT ); Wed, 26 Oct 2016 00:12:59 -0400 DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 4568261569 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=sricharan@codeaurora.org From: "Sricharan" To: "'Stanimir Varbanov'" , , , , , , References: <1477304297-5248-1-git-send-email-sricharan@codeaurora.org> <1477304297-5248-2-git-send-email-sricharan@codeaurora.org> In-Reply-To: Subject: RE: [PATCH 1/3] clk: qcom: gdsc: Add support for gdscs with HW control Date: Wed, 26 Oct 2016 09:42:51 +0530 Message-ID: <001201d22f3f$3bb92440$b32b6cc0$@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 15.0 Thread-Index: AQG+FfkBp35ZYGVHUWKvPRGPq/wjNgLVaGxUAWNvwvCgwIsewA== Content-Language: en-us Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1527 Lines: 51 Hi Stan, >Hi Sricharan, > >On 10/24/2016 01:18 PM, Sricharan R wrote: >> From: Rajendra Nayak >> >> Some GDSCs might support a HW control mode, where in the power >> domain (gdsc) is brought in and out of low power state (while >> unsued) without any SW assistance, saving power. >> Such GDSCs can be configured in a HW control mode when powered on >> until they are explicitly requested to be powered off by software. >> >> Signed-off-by: Rajendra Nayak >> Signed-off-by: Sricharan R >> --- >> drivers/clk/qcom/gdsc.c | 15 +++++++++++++++ >> drivers/clk/qcom/gdsc.h | 1 + >> 2 files changed, 16 insertions(+) >> >> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c >> index f12d7b2..a5e1c8c 100644 >> --- a/drivers/clk/qcom/gdsc.c >> +++ b/drivers/clk/qcom/gdsc.c >> @@ -55,6 +55,13 @@ static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg) >> return !!(val & PWR_ON_MASK); >> } >> >> +static int gdsc_hwctrl(struct gdsc *sc, bool en) >> +{ >> + u32 val = en ? HW_CONTROL_MASK : 0; >> + >> + return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val); >> +} >> + >> static int gdsc_toggle_logic(struct gdsc *sc, bool en) >> { >> int ret; >> @@ -164,6 +171,10 @@ static int gdsc_enable(struct generic_pm_domain *domain) >> */ >> udelay(1); >> >> + /* Turn on HW trigger mode if supported */ >> + if (sc->flags & HW_CTRL) >> + gdsc_hwctrl(sc, true); > Sure, will add the check. Regards, Sricharan