Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1034070AbcJ0OZc (ORCPT ); Thu, 27 Oct 2016 10:25:32 -0400 Received: from userp1040.oracle.com ([156.151.31.81]:34199 "EHLO userp1040.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1034051AbcJ0OZ3 (ORCPT ); Thu, 27 Oct 2016 10:25:29 -0400 Subject: Re: [Xen-devel] [PATCH 8/8] xen/pvh: Enable CPU hotplug To: Andrew Cooper , david.vrabel@citrix.com, JGross@suse.com References: <1476468318-24422-1-git-send-email-boris.ostrovsky@oracle.com> <1476468318-24422-9-git-send-email-boris.ostrovsky@oracle.com> Cc: xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, roger.pau@citrix.com, Jan Beulich From: Boris Ostrovsky Message-ID: <846901a2-06c1-931f-9933-bda4696e2e40@oracle.com> Date: Thu, 27 Oct 2016 10:25:13 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Source-IP: aserv0021.oracle.com [141.146.126.233] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1635 Lines: 44 On 10/14/2016 03:01 PM, Boris Ostrovsky wrote: > On 10/14/2016 02:41 PM, Andrew Cooper wrote: >> On 14/10/16 19:05, Boris Ostrovsky wrote: >>> PVH guests don't receive ACPI hotplug interrupts and therefore >>> need to monitor xenstore for CPU hotplug event. >> Why not? If they don't, they should. As we are providing ACPI anyway, >> we should provide all bits of it. > > We don't have IOAPIC, which is how these interrupts are typically > delivered. I suppose we might be able to specify it as something else. > > I'll look into this. (+Jan) Yes, we can do this. The main issue is how to deal with event registers (i.e FADT.x_pm1a_evt_blk) and AML's PRST region (which specifies online CPU map). Currently these are accessed via IO space and are handled by qemu. There are a couple of ways to deal with this that I can see. 1. We can implement ioreq handling in the hypervisor, there are only a few addresses that need handling. 2. We can implement those registers in memory space and have libxl update them them on a hotplug command. This appears to be possible because these registers mostly just consume writes without side effects so they can be simple memory locations. The one exception is updating status bits (they are cleared by writing 1s) but I think we can do this from the AML. Other than that the only other thing is setting up an event channel between the toolstack and the guest (either via xenstore or perhaps by having a reserved port for SCI). I have a prototype with (2) (except for the bit clearing part) but I want to hear comments on this approach before I write proper patches. -boris