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Date: Thu, 27 Oct 2016 16:38:13 +0200 (CEST)
From: Thomas Gleixner <tglx@linutronix.de>
To: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
cc: mingo@redhat.com, hpa@zytor.com, x86@kernel.org, bp@suse.de,
        dave.hansen@linux.intel.com, lukasz.daniluk@intel.com,
        james.h.cownie@intel.com, jacob.jun.pan@intel.com, Piotr.Luc@intel.com,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot
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References: <1477576923-3244-1-git-send-email-grzegorz.andrejczuk@intel.com> <1477576923-3244-3-git-send-email-grzegorz.andrejczuk@intel.com>
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On Thu, 27 Oct 2016, Grzegorz Andrejczuk wrote:
> +#ifdef CONFIG_X86_64
> +static int phi_r3mwait_disabled __read_mostly;
> +
> +static int __init phir3mwait_disable(char *__unused)
> +{
> +	phi_r3mwait_disabled = 1;
> +	pr_warn("x86/phir3mwait: Disabled ring 3 MWAIT for Xeon Phi");

Why would that be a warning? The sysadmin added the command line switch, so
why does he needs to be warned?

> +	return 1;
> +}
> +__setup("phir3mwait=disable", phir3mwait_disable);
> +
> +static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
> +{
> +	u64 msr;
> +
> +	rdmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
> +
> +	if (phi_r3mwait_disabled) {
> +		msr &= ~MSR_PHI_MISC_THD_FEATURE_R3MWAIT;
> +		wrmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
> +	} else {
> +		msr |= MSR_PHI_MISC_THD_FEATURE_R3MWAIT;
> +		wrmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
> +	}

	if (phi_r3mwait_disabled)
		msr &= ~MSR_PHI_MISC_THD_FEATURE_R3MWAIT;
	else
		msr |= MSR_PHI_MISC_THD_FEATURE_R3MWAIT;

	wrmsrl(MSR_PHI_MISC_THD_FEATURE, msr);

Would be too simple and obvious, right? You still can add the extra bits of
setting the capability flag into the else path.

>  	init_intel_energy_perf(c);
> +
> +	/*
> +	* Setting ring 3 MONITOR/MWAIT for thread
> +	* when CPU is Xeon Phi Family x200 (KnightsLanding).
> +	*/
> +	if (c->x86 == 6 && c->x86_model == INTEL_FAM6_XEON_PHI_KNL)

Please move this conditional into the probe function.

> +		probe_xeon_phi_r3mwait(c);

Can you please check with your hardware people, whether this function is
somewhere detectable. bit 0 of the MISC_*FEATURE* MSR (Ring 3 CPUID fault
enable) is detectable via the PLATFORM_INFO MSR. I would be surprised if
this thing is not detectable in some way.

I really prefer detectable things over hardcoded crap which depends on
model information.

Thanks,

	tglx