Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755905AbcJ0Qxu convert rfc822-to-8bit (ORCPT ); Thu, 27 Oct 2016 12:53:50 -0400 Received: from mga07.intel.com ([134.134.136.100]:13308 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755722AbcJ0Qxt (ORCPT ); Thu, 27 Oct 2016 12:53:49 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,553,1473145200"; d="scan'208";a="1051234646" From: "Andrejczuk, Grzegorz" To: Thomas Gleixner CC: "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "bp@suse.de" , "dave.hansen@linux.intel.com" , "Daniluk, Lukasz" , "Cownie, James H" , "Pan, Jacob jun" , "Luc, Piotr" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot Thread-Topic: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot Thread-Index: AQHSMFrIx4R57b7tPkCU8e7bNAqHeqC8TgSAgAA1OIA= Date: Thu, 27 Oct 2016 16:53:45 +0000 Message-ID: References: <1477576923-3244-1-git-send-email-grzegorz.andrejczuk@intel.com> <1477576923-3244-3-git-send-email-grzegorz.andrejczuk@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 885 Lines: 19 > > init_intel_energy_perf(c); > > + > > + /* > > + * Setting ring 3 MONITOR/MWAIT for thread > > + * when CPU is Xeon Phi Family x200 (KnightsLanding). > > + */ > > + if (c->x86 == 6 && c->x86_model == INTEL_FAM6_XEON_PHI_KNL) > > Please move this conditional into the probe function. > > > + probe_xeon_phi_r3mwait(c); > > Can you please check with your hardware people, whether this function is somewhere detectable. bit 0 of the MISC_*FEATURE* MSR (Ring 3 CPUID fault > enable) is detectable via the PLATFORM_INFO MSR. I would be surprised if this thing is not detectable in some way. > > I really prefer detectable things over hardcoded crap which depends on model information. I asked hardware people and MSR 0x140 should be called MSR_MISC_FEATURE_ENABLES and there is no other feature MSR indicating that this bit can be set. Unfortunately hardcoded crap has to be used.