Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S942302AbcJ0SY4 (ORCPT ); Thu, 27 Oct 2016 14:24:56 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:44636 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935747AbcJ0SYy (ORCPT ); Thu, 27 Oct 2016 14:24:54 -0400 Date: Thu, 27 Oct 2016 20:22:07 +0200 (CEST) From: Thomas Gleixner To: "Andrejczuk, Grzegorz" cc: "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "bp@suse.de" , "dave.hansen@linux.intel.com" , "Daniluk, Lukasz" , "Cownie, James H" , "Pan, Jacob jun" , "Luc, Piotr" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot In-Reply-To: Message-ID: References: <1477576923-3244-1-git-send-email-grzegorz.andrejczuk@intel.com> <1477576923-3244-3-git-send-email-grzegorz.andrejczuk@intel.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1233 Lines: 33 On Thu, 27 Oct 2016, Andrejczuk, Grzegorz wrote: > > > init_intel_energy_perf(c); > > > + > > > + /* > > > + * Setting ring 3 MONITOR/MWAIT for thread > > > + * when CPU is Xeon Phi Family x200 (KnightsLanding). > > > + */ > > > + if (c->x86 == 6 && c->x86_model == INTEL_FAM6_XEON_PHI_KNL) > > > > Please move this conditional into the probe function. > > > > > + probe_xeon_phi_r3mwait(c); > > > > Can you please check with your hardware people, whether this function > > is somewhere detectable. bit 0 of the MISC_*FEATURE* MSR (Ring 3 CPUID > > fault enable) is detectable via the PLATFORM_INFO MSR. I would be > > surprised if this thing is not detectable in some way. > > > > I really prefer detectable things over hardcoded crap which depends on > > model information. > > I asked hardware people and MSR 0x140 should be called > MSR_MISC_FEATURE_ENABLES and there is no other feature MSR indicating > that this bit can be set. Unfortunately hardcoded crap has to be used. Can you please tell your hardware folks, that non discoverable features are a horror? We really need unique detection of features across all the various cpu platforms. Making stuff depend on models, stepping results in a nightmare. Thanks, tglx