Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1034099AbcJ1Q5I (ORCPT ); Fri, 28 Oct 2016 12:57:08 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:33129 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1032815AbcJ1Q5E (ORCPT ); Fri, 28 Oct 2016 12:57:04 -0400 From: Joshua Clayton To: Alan Tull , Moritz Fischer Cc: Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Fabio Estevam , Russell King , Joshua Clayton , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 5/5] fpga manager: cyclone-ps-spi: make delay variable Date: Fri, 28 Oct 2016 09:56:42 -0700 Message-Id: <2239ffc8aba7d053825d2bea122a3c16cdd9f6e1.1477669745.git.stillcompiling@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1856 Lines: 53 The status pin may not show ready in the time described in the Altetera manual. check the value several times before giving up For the hardware I am working on, the status pin takes 250 us, 5 times as long as described by Altera. Signed-off-by: Joshua Clayton --- drivers/fpga/cyclone-ps-spi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/fpga/cyclone-ps-spi.c b/drivers/fpga/cyclone-ps-spi.c index 4b70d5c..c368223 100644 --- a/drivers/fpga/cyclone-ps-spi.c +++ b/drivers/fpga/cyclone-ps-spi.c @@ -20,6 +20,7 @@ #define FPGA_RESET_TIME 50 /* time in usecs to trigger FPGA config */ -#define FPGA_MIN_DELAY 250 /* min usecs to wait for config status */ +#define FPGA_MIN_DELAY 50 /* min usecs to wait for config status */ +#define FPGA_MAX_DELAY 1000 /* max usecs to wait for config status */ struct cyclonespi_conf { struct gpio_desc *config; @@ -42,6 +43,7 @@ static int cyclonespi_write_init(struct fpga_manager *mgr, u32 flags, const char *buf, size_t count) { struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv; + int i; if (flags & FPGA_MGR_PARTIAL_RECONFIG) { dev_err(&mgr->dev, "Partial reconfiguration not supported.\n"); @@ -56,13 +58,14 @@ static int cyclonespi_write_init(struct fpga_manager *mgr, u32 flags, } gpiod_set_value(conf->config, 1); - usleep_range(FPGA_MIN_DELAY, FPGA_MIN_DELAY + 20); - if (gpiod_get_value(conf->status) == 0) { - dev_err(&mgr->dev, "Status pin not ready.\n"); - return -EIO; + for (i = 0; i < (FPGA_MAX_DELAY / FPGA_MIN_DELAY); i++) { + usleep_range(FPGA_MIN_DELAY, FPGA_MIN_DELAY + 20); + if (gpiod_get_value(conf->status)) + return 0; } - return 0; + dev_err(&mgr->dev, "Status pin not ready.\n"); + return -EIO; } static void rev_buf(void *buf, size_t len) -- 2.7.4