Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757077AbcJ2Ga5 (ORCPT ); Sat, 29 Oct 2016 02:30:57 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:7023 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756882AbcJ2Gay (ORCPT ); Sat, 29 Oct 2016 02:30:54 -0400 From: Jiancheng Xue To: , , , CC: , , , , , , , , , Jiancheng Xue Subject: [PATCH 0/2] clk: hisilicon: add CRG driver for Hi3798CV200 and Hi3516CV300 SoCs Date: Sat, 29 Oct 2016 14:13:36 +0800 Message-ID: <1477721618-10809-1-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.212.71] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1151 Lines: 24 Add CRG driver for Hi3798CV200 and Hi3516CV200 SoCs. Jiancheng Xue (2): clk: hisilicon: add CRG driver for Hi3798CV200 SoC clk: hisilicon: add CRG driver for Hi3516CV300 SoC .../clock/{hi3519-crg.txt => hisi-crg.txt} | 12 +- drivers/clk/hisilicon/Kconfig | 16 + drivers/clk/hisilicon/Makefile | 2 + drivers/clk/hisilicon/crg-hi3516cv300.c | 330 ++++++++++++++++++++ drivers/clk/hisilicon/crg-hi3798cv200.c | 337 +++++++++++++++++++++ drivers/clk/hisilicon/crg.h | 34 +++ include/dt-bindings/clock/hi3516cv300-clock.h | 48 +++ include/dt-bindings/clock/histb-clock.h | 66 ++++ 8 files changed, 841 insertions(+), 4 deletions(-) rename Documentation/devicetree/bindings/clock/{hi3519-crg.txt => hisi-crg.txt} (80%) create mode 100644 drivers/clk/hisilicon/crg-hi3516cv300.c create mode 100644 drivers/clk/hisilicon/crg-hi3798cv200.c create mode 100644 drivers/clk/hisilicon/crg.h create mode 100644 include/dt-bindings/clock/hi3516cv300-clock.h create mode 100644 include/dt-bindings/clock/histb-clock.h -- 1.9.1