Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934923AbcJaQ0g (ORCPT ); Mon, 31 Oct 2016 12:26:36 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:6140 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932177AbcJaQ0e (ORCPT ); Mon, 31 Oct 2016 12:26:34 -0400 Date: Mon, 31 Oct 2016 16:26:24 +0000 From: "Maciej W. Rozycki" To: Ralf Baechle CC: , Subject: [PATCH 2/4] MIPS: Remove FIR from ISA I FP signal context In-Reply-To: Message-ID: References: User-Agent: Alpine 2.00 (DEB 1167 2008-08-23) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-Originating-IP: [10.20.78.238] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1158 Lines: 30 Complement commit e50c0a8fa60d ("Support the MIPS32 / MIPS64 DSP ASE.") and remove the Floating Point Implementation Register (FIR) from the FP register set recorded in a signal context with MIPS I processors too, in line with the change applied to r4k_fpu.S. The `sc_fpc_eir' slot is unused according to our current ABI and the FIR register is read-only and always directly accessible from user software. Signed-off-by: Maciej W. Rozycki --- linux-mips-isa1-sig-fp-context-dsp.patch Index: linux-sfr-test/arch/mips/kernel/r2300_fpu.S =================================================================== --- linux-sfr-test.orig/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:17:38.000000000 +0100 +++ linux-sfr-test/arch/mips/kernel/r2300_fpu.S 2016-10-22 02:19:40.565112000 +0100 @@ -64,13 +64,9 @@ LEAF(_save_fp_context) EX(swc1 $f29,(SC_FPREGS+232)(a0)) EX(swc1 $f30,(SC_FPREGS+240)(a0)) EX(swc1 $f31,(SC_FPREGS+248)(a0)) - EX(sw t1,(SC_FPC_CSR)(a0)) - cfc1 t0,$0 # implementation/version jr ra + EX(sw t1,(SC_FPC_CSR)(a0)) .set pop - .set nomacro - EX(sw t0,(SC_FPC_EIR)(a0)) - .set macro END(_save_fp_context) /*