From: Eric Anholt <eric@anholt.net>
To: Michael Zoran <mzoran@crowfest.net>, gregkh@linuxfoundation.org
Cc: swarren@wwwdotorg.org, lee@kernel.org, mzoran@crowfest.net,
        daniels@collabora.com, noralf@tronnes.org, popcornmix@gmail.com,
        linux-rpi-kernel@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org, devel@driverdev.osuosl.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] staging: vc04_services: setup DMA and coherent mask
In-Reply-To: <20161028171159.23973-1-mzoran@crowfest.net>
References: <20161028171159.23973-1-mzoran@crowfest.net>
User-Agent: Notmuch/0.22.2+1~gb0bcfaa (http://notmuchmail.org) Emacs/24.5.1 (x86_64-pc-linux-gnu)
Date: Mon, 31 Oct 2016 11:36:31 -0700
Message-ID: <87twbsqsb4.fsf@eliezer.anholt.net>
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Michael Zoran <mzoran@crowfest.net> writes:

> Setting the DMA mask is optional on 32 bit but
> is mandatory on 64 bit.  Set the DMA mask and coherent
> to force all DMA to be in the 32 bit address space.
>
> This is considered a "good practice" and most drivers
> already do this.
>
> Signed-off-by: Michael Zoran <mzoran@crowfest.net>
> ---
>  .../staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c | 10 ++++=
++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835=
_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
> index a5afcc5..6fa2b5a 100644
> --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
> +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
> @@ -97,6 +97,16 @@ int vchiq_platform_init(struct platform_device *pdev, =
VCHIQ_STATE_T *state)
>  	int slot_mem_size, frag_mem_size;
>  	int err, irq, i;
>=20=20
> +	/*
> +	 * Setting the DMA mask is necessary in the 64 bit environment.
> +	 * It isn't necessary in a 32 bit environment but is considered
> +	 * a good practice.
> +	 */
> +	err =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));

I think a better comment here would be simply:

/* VCHI messages between the CPU and firmware use 32-bit bus addresses. */

explaining why the value is chosen (once you know that the 32 bit
restriction exists, reporting it is obviously needed).  I'm curious,
though: what failed when you didn't set it?

> +
> +	if (err < 0)
> +		return err;
> +
>  	(void)of_property_read_u32(dev->of_node, "cache-line-size",
>  				   &g_cache_line_size);
>  	g_fragments_size =3D 2 * g_cache_line_size;
> --=20
> 2.10.1

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