Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753456AbcKARIr (ORCPT ); Tue, 1 Nov 2016 13:08:47 -0400 Received: from mga04.intel.com ([192.55.52.120]:39161 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753235AbcKARIo (ORCPT ); Tue, 1 Nov 2016 13:08:44 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,580,1473145200"; d="scan'208";a="186391613" From: Bin Gao To: Thomas Gleixner , Ingo Molnar , H Peter Anvin , x86@kernel.org Cc: Peter Zijlstra , linux-kernel@vger.kernel.org, Bin Gao Subject: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs Date: Tue, 1 Nov 2016 10:14:42 -0700 Message-Id: <1478020482-231459-3-git-send-email-bin.gao@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1478020482-231459-1-git-send-email-bin.gao@intel.com> References: <1478020482-231459-1-git-send-email-bin.gao@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2782 Lines: 80 With X86_FEATURE_TSC_RELIABLE is split into X86_FEATURE_TSC_KNOWN_FREQ and X86_FEATURE_TSC_KNOWN_FREQ, some platforms with reliable and frequency-known TSC have to be marked with these new flags. These platforms are Intel processors/SoCs supporting getting TSC frequency by MSR or CPUID. Signed-off-by: Bin Gao --- arch/x86/kernel/tsc.c | 9 +++++++++ arch/x86/kernel/tsc_msr.c | 4 ++++ arch/x86/platform/intel-mid/mfld.c | 5 +++-- arch/x86/platform/intel-mid/mrfld.c | 4 ++-- 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index b4c82f8..4197768 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void) } } + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); + + /* + * For Atom SoCs TSC is the only reliable clocksource. + * Mark TSC reliable so no watchdog on it. + */ + if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT) + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); + return crystal_khz * ebx_numerator / eax_denominator; } diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c index 0fe720d..d6aa75a 100644 --- a/arch/x86/kernel/tsc_msr.c +++ b/arch/x86/kernel/tsc_msr.c @@ -100,5 +100,9 @@ unsigned long cpu_khz_from_msr(void) #ifdef CONFIG_X86_LOCAL_APIC lapic_timer_frequency = (freq * 1000) / HZ; #endif + + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); + return res; } diff --git a/arch/x86/platform/intel-mid/mfld.c b/arch/x86/platform/intel-mid/mfld.c index 1eb47b6..3fa41b4 100644 --- a/arch/x86/platform/intel-mid/mfld.c +++ b/arch/x86/platform/intel-mid/mfld.c @@ -49,8 +49,9 @@ static unsigned long __init mfld_calibrate_tsc(void) fast_calibrate = ratio * fsb; pr_debug("read penwell tsc %lu khz\n", fast_calibrate); lapic_timer_frequency = fsb * 1000 / HZ; - /* mark tsc clocksource as reliable */ - set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE); + + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); return fast_calibrate; } diff --git a/arch/x86/platform/intel-mid/mrfld.c b/arch/x86/platform/intel-mid/mrfld.c index 59253db..9477b7e 100644 --- a/arch/x86/platform/intel-mid/mrfld.c +++ b/arch/x86/platform/intel-mid/mrfld.c @@ -78,8 +78,8 @@ static unsigned long __init tangier_calibrate_tsc(void) pr_debug("Setting lapic_timer_frequency = %d\n", lapic_timer_frequency); - /* mark tsc clocksource as reliable */ - set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE); + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); return fast_calibrate; } -- 1.9.1