Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754637AbcKAXZt (ORCPT ); Tue, 1 Nov 2016 19:25:49 -0400 Received: from gloria.sntech.de ([95.129.55.99]:36335 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751980AbcKAXZs (ORCPT ); Tue, 1 Nov 2016 19:25:48 -0400 From: Heiko Stuebner To: Xing Zheng Cc: dianders@google.com, zhangqing@rock-chips.com, huangtao@rock-chips.com, briannorris@google.com, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] clk: rockchip: optimize the configuration for 800MHz and 1GHz on RK3399 Date: Wed, 02 Nov 2016 00:25:37 +0100 Message-ID: <37901081.P92AxpVH96@phil> User-Agent: KMail/5.2.3 (Linux/4.7.0-1-amd64; KDE/5.26.0; x86_64; ; ) In-Reply-To: <1477970526-26388-1-git-send-email-zhengxing@rock-chips.com> References: <1477970526-26388-1-git-send-email-zhengxing@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 573 Lines: 19 Am Dienstag, 1. November 2016, 11:22:06 CET schrieb Xing Zheng: > Usually, the 800MHz and 1GHz are supplied for CPLL and NPLL in the RK3399. > But dues to the carelessly copying from RK3036 when the RK3399 bringing up, > the refdiv == 6, it will increase the lock time, and it is not an optimal > configuration. > > Please let's fix them for the lock time and jitter are lower: > 800 MHz: > - FVCO == 2.4 GHz, revdiv == 1. > 1 GHz: > - FVCO == 3 GHz, revdiv == 1. > > Signed-off-by: Xing Zheng applied to my clk-branch for 4.10 Thanks Heiko