Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933376AbcKCWX0 (ORCPT ); Thu, 3 Nov 2016 18:23:26 -0400 Received: from smtprelay4.synopsys.com ([198.182.47.9]:40735 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932875AbcKCWXY (ORCPT ); Thu, 3 Nov 2016 18:23:24 -0400 Subject: Re: [PATCH v2 01/10] ARC: timer: rtc: implement read loop in "C" vs. inline asm To: Daniel Lezcano References: <1478208701-30923-1-git-send-email-vgupta@synopsys.com> <1478208701-30923-2-git-send-email-vgupta@synopsys.com> <20161103215221.GM1859@mai> CC: Noam Camus , , , , , Newsgroups: gmane.linux.kernel.stable,gmane.linux.kernel.arc,gmane.linux.kernel From: Vineet Gupta Message-ID: <952c1d98-2827-5127-2440-edab342e6b77@synopsys.com> Date: Thu, 3 Nov 2016 15:23:09 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <20161103215221.GM1859@mai> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.10.161.44] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1952 Lines: 58 On 11/03/2016 02:52 PM, Daniel Lezcano wrote: > On Thu, Nov 03, 2016 at 02:31:32PM -0700, Vineet Gupta wrote: >> The current code doesn't even compile .... > > Give a better description in the log, especially if this patch is supposed to > go to stable@ OK. > >> CC: stable@vger.kernel.org >> Signed-off-by: Vineet Gupta >> --- >> arch/arc/kernel/time.c | 19 +++++++++++-------- >> 1 file changed, 11 insertions(+), 8 deletions(-) >> >> diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c >> index f927b8dc6edd..1a117b999c0c 100644 >> --- a/arch/arc/kernel/time.c >> +++ b/arch/arc/kernel/time.c >> @@ -152,14 +152,17 @@ static cycle_t arc_read_rtc(struct clocksource *cs) >> cycle_t full; >> } stamp; >> >> - >> - __asm__ __volatile( >> - "1: \n" >> - " lr %0, [AUX_RTC_LOW] \n" >> - " lr %1, [AUX_RTC_HIGH] \n" >> - " lr %2, [AUX_RTC_CTRL] \n" >> - " bbit0.nt %2, 31, 1b \n" >> - : "=r" (stamp.low), "=r" (stamp.high), "=r" (status)); >> + /* >> + * hardware has an internal state machine which tracks readout of >> + * low/high and updates the CTRL.status if >> + * - interrupt/exception taken between the two reads >> + * - high increments after low has been read >> + */ >> + do { >> + stamp.low = read_aux_reg(AUX_RTC_LOW); >> + stamp.high = read_aux_reg(AUX_RTC_HIGH); >> + status = read_aux_reg(AUX_RTC_CTRL); >> + } while (!(status & _BITUL(31))); > > Is the condition correct ? If I refer to your previous answer, the bit will be > set for status if the counter wrapped up. So in this case, we won't exit the > loop until we wrap up, no ? No thats not what I meant. Bit being set there means things are fine (no interrupt taken, no increment of high after low was readetc). All I changed here was use of 0x8000_0000 to the macro. BBIT0 in assembler means branch if bit was clear. > >> return stamp.full; >> } >> -- >> 2.7.4 >>