Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752726AbcKGMKO (ORCPT ); Mon, 7 Nov 2016 07:10:14 -0500 Received: from regular1.263xmail.com ([211.150.99.135]:59865 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751296AbcKGMKI (ORCPT ); Mon, 7 Nov 2016 07:10:08 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED4: 1 X-RL-SENDER: wulf@rock-chips.com X-FST-TO: kishon@ti.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: wulf@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: William Wu To: kishon@ti.com, heiko@sntech.de Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, robh+dt@kernel.org, frank.wang@rock-chips.com, huangtao@rock-chips.com, dianders@google.com, briannorris@google.com, groeck@google.com, wulf@rock-chips.com Subject: [PATCH v3 2/2] arm64: dts: rockchip: add usb2-phy otg-port support for rk3399 Date: Mon, 7 Nov 2016 20:08:49 +0800 Message-Id: <1478520529-8869-3-git-send-email-wulf@rock-chips.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1478520529-8869-1-git-send-email-wulf@rock-chips.com> References: <1478520529-8869-1-git-send-email-wulf@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1563 Lines: 56 Add otg-port nodes for both u2phy0 and u2phy1. The otg-port can be used for USB2.0 part of USB3.0 OTG controller. Signed-off-by: William Wu --- Changes in v3: - None Changes in v2: - None arch/arm64/boot/dts/rockchip/rk3399.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index b65c193..ea2df51 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1095,6 +1095,17 @@ clock-output-names = "clk_usbphy0_480m"; status = "disabled"; + u2phy0_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + + u2phy0_host: host-port { #phy-cells = <0>; interrupts = ; @@ -1112,6 +1123,16 @@ clock-output-names = "clk_usbphy1_480m"; status = "disabled"; + u2phy1_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + u2phy1_host: host-port { #phy-cells = <0>; interrupts = ; -- 2.0.0