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Date: Mon, 7 Nov 2016 12:27:53 +0100
From: Thierry Reding <thierry.reding@gmail.com>
To: Mirza Krak <mirza.krak@gmail.com>
Cc: swarren@wwwdotorg.org, jonathanh@nvidia.com, gnurou@gmail.com,
        linux@armlinux.org.uk, pdeschrijver@nvidia.com, pgaikwad@nvidia.com,
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        mark.rutland@arm.com, devicetree@vger.kernel.org,
        linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
Message-ID: <20161107112753.GA28616@ulmo.ba.sec>
References: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
 <1478507405-13204-2-git-send-email-mirza.krak@gmail.com>
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On Mon, Nov 07, 2016 at 09:30:00AM +0100, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak@gmail.com>
>=20
> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
> is max rate.
>=20
> The maximum rate value of 92 MHz is pulled from the downstream L4T
> kernel.
>=20
> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
> Acked-by: Jon Hunter <jonathanh@nvidia.com>
> ---
>=20
> Changes in v2:
> - no changes
>=20
> Changes in v3:
> - Added comment in commit message where I got the maximum rates from.
>=20
> Changes in V4:
> - no changes

Applied, thanks.

Thierry

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