Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932578AbcKGNUc (ORCPT ); Mon, 7 Nov 2016 08:20:32 -0500 Received: from mail-wm0-f43.google.com ([74.125.82.43]:35204 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932274AbcKGNFd (ORCPT ); Mon, 7 Nov 2016 08:05:33 -0500 From: Alexandre Bailon To: david@lechnology.com, b-liu@ti.com, balbi@kernel.org Cc: kishon@ti.com, khilman@baylibre.com, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, nsekhar@ti.com, Alexandre Bailon Subject: [PATCH v5 2/4] phy: da8xx-usb: Configure CFGCHIP2 to support OTG workaround Date: Mon, 7 Nov 2016 14:05:06 +0100 Message-Id: <1478523908-4383-3-git-send-email-abailon@baylibre.com> X-Mailer: git-send-email 2.7.3 In-Reply-To: <1478523908-4383-1-git-send-email-abailon@baylibre.com> References: <1478523908-4383-1-git-send-email-abailon@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1204 Lines: 39 If we configure the da8xx OTG phy in OTG mode, neither device or host mode will work. That is because the PHY is not able to detect and notify the driver that value of ID pin changed. To work despite this hardware limitation, the da8xx glue implement a workaround. But to work, the workaround require the VBUS sense and the session end comparator to enabled. Enable them if the phy is configured in OTG mode. Signed-off-by: Alexandre Bailon --- drivers/phy/phy-da8xx-usb.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/phy/phy-da8xx-usb.c b/drivers/phy/phy-da8xx-usb.c index 32ae78c..089c13b 100644 --- a/drivers/phy/phy-da8xx-usb.c +++ b/drivers/phy/phy-da8xx-usb.c @@ -23,6 +23,8 @@ #include #include +#define PHY_INIT_BITS (CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN) + struct da8xx_usb_phy { struct phy_provider *phy_provider; struct phy *usb11_phy; @@ -207,6 +209,9 @@ static int da8xx_usb_phy_probe(struct platform_device *pdev) dev_warn(dev, "Failed to create usb20 phy lookup\n"); } + regmap_write_bits(d_phy->regmap, CFGCHIP(2), + PHY_INIT_BITS, PHY_INIT_BITS); + return 0; } -- 2.7.3