Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753223AbcKHDWs (ORCPT ); Mon, 7 Nov 2016 22:22:48 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:9586 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752175AbcKHDWn (ORCPT ); Mon, 7 Nov 2016 22:22:43 -0500 From: "zhichang.yuan" To: , , , , , , , CC: , , , , , , , , , , , , , , , "zhichang.yuan" Subject: [PATCH V5 0/3] ARM64 LPC: legacy ISA I/O support Date: Tue, 8 Nov 2016 11:47:06 +0800 Message-ID: <1478576829-112707-1-git-send-email-yuanzhichang@hisilicon.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3820 Lines: 85 This patch supports the IPMI-bt device attached to the Low-Pin-Count interface implemented on Hisilicon Hip06 SoC. ----------- | LPC host| | | ----------- | _____________V_______________LPC | | V V ------------ | BT(ipmi)| ------------ When master accesses those periperals beneath the Hip06 LPC, a specific LPC driver is needed to make LPC host generate the standard LPC I/O cycles with the target periperals'I/O port addresses. But on curent arm64 world, there is no real I/O accesses. All the I/O operations through in/out pair are based on MMIO which is not satisfied the I/O mechanism on Hip06 LPC. To solve this issue and keep the relevant existing peripherals' driver unchanged, this patch set redefines the in/out pair to support both the IO operations for Hip06 LPC and the original MMIO. The way specific to Hip06 is named as indirect-IO in this patchset. Changes from V4: - Some revises based on the comments from Bjorn, Rob on V4; - Fixed the compile error on some platforms, such as openrisc; Changes from V3: - UART support deferred to a separate patchset; This patchset only support ipmi device under LPC; - LPC bus I/O range is fixed to 0 ~ (PCIBIOS_MIN_IO - 1), which is separeted from PCI/PCIE PIO space; - Based on Arnd's remarks, removed the ranges property from Hip06 lpc dts and added a new fixup function, of_isa_indirect_io(), to get the I/O address directly from LPC dts configurations; - Support in(w,l)/out(w,l) for Hip06 lpc I/O; - Decouple the header file dependency on the gerenic io.h by defining in/out as normal functions in c file; - removed unused macro definitions in the LPC driver; Changes from V2: - Support the PIO retrieval from the linux PIO generated by pci_address_to_pio. This method replace the 4K PIO reservation in V2; - Support the flat-tree earlycon; - Some revises based on Arnd's remarks; - Make sure the linux PIO range allocated to Hip06 LPC peripherals starts from non-ZERO; Changes from V1: - Support the ACPI LPC device; - Optimize the dts LPC driver in ISA compatible mode; - Reserve the IO range below 4K in avoid the possible conflict with PCI host IO ranges; - Support the LPC uart and relevant earlycon; Signed-off-by: Zhichang Yuan zhichang.yuan (3): ARM64 LPC: Indirect ISA port IO introduced ARM64 LPC: Add missing range exception for special ISA ARM64 LPC: LPC driver implementation on Hip06 .../arm/hisilicon/hisilicon-low-pin-count.txt | 31 ++ MAINTAINERS | 8 + arch/arm64/Kconfig | 6 + arch/arm64/include/asm/extio.h | 94 ++++ arch/arm64/include/asm/io.h | 35 ++ arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/extio.c | 52 +++ drivers/bus/Kconfig | 8 + drivers/bus/Makefile | 1 + drivers/bus/hisi_lpc.c | 501 +++++++++++++++++++++ drivers/of/address.c | 56 ++- drivers/pci/pci.c | 6 +- include/linux/of_address.h | 17 + include/linux/pci.h | 8 + 14 files changed, 820 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt create mode 100644 arch/arm64/include/asm/extio.h create mode 100644 arch/arm64/kernel/extio.c create mode 100644 drivers/bus/hisi_lpc.c -- 1.9.1