Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753380AbcKHPc4 (ORCPT ); Tue, 8 Nov 2016 10:32:56 -0500 Received: from mail-vk0-f49.google.com ([209.85.213.49]:36076 "EHLO mail-vk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751716AbcKHPcv (ORCPT ); Tue, 8 Nov 2016 10:32:51 -0500 MIME-Version: 1.0 In-Reply-To: <1478585533-19406-2-git-send-email-ricardo.neri-calderon@linux.intel.com> References: <1478585533-19406-1-git-send-email-ricardo.neri-calderon@linux.intel.com> <1478585533-19406-2-git-send-email-ricardo.neri-calderon@linux.intel.com> From: Andy Lutomirski Date: Tue, 8 Nov 2016 07:32:29 -0800 Message-ID: Subject: Re: [PATCH 1/4] x86/cpufeature: Add User-Mode Instruction Prevention definitions To: Ricardo Neri Cc: Ingo Molnar , Thomas Gleixner , "H. Peter Anvin" , "linux-kernel@vger.kernel.org" , X86 ML , "linux-doc@vger.kernel.org" , Andy Lutomirski , Andrew Morton , Borislav Petkov , Brian Gerst , Chen Yucong , Chris Metcalf , Dave Hansen , Fenghua Yu , Huang Rui , Jiri Slaby , Jonathan Corbet , "Michael S . Tsirkin" , Paul Gortmaker , Peter Zijlstra , "Ravi V . Shankar" , Shuah Khan , Vlastimil Babka Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2966 Lines: 70 On Mon, Nov 7, 2016 at 10:12 PM, Ricardo Neri wrote: > User-Mode Instruction Prevention (UMIP) is a security feature present in > new Intel Processors. If enabled, it prevents the execution of certain > instructions if the Current Privilege Level (CPL) is greater than 0. If > these instructions were executed while in CPL > 0, user space applications > could have access to system-wide settings such as the global and local > descriptor tables, the task register and the interrupt descriptor table. > > These are the instructions covered by UMIP: > * SGDT - Store Global Descriptor Table > * SIDT - Store Interrupt Descriptor Table > * SLDT - Store Local Descriptor Table > * SMSW - Store Machine Status Word > * STR - Store Task Register > > If any of these instructions is executed with CPL > 0, a general protection > exception is issued when UMIP is enbled. > > Cc: Andy Lutomirski > Cc: Andrew Morton > Cc: Borislav Petkov > Cc: Brian Gerst > Cc: Chen Yucong > Cc: Chris Metcalf > Cc: Dave Hansen > Cc: Fenghua Yu > Cc: Huang Rui > Cc: Jiri Slaby > Cc: Jonathan Corbet > Cc: Michael S. Tsirkin > Cc: Paul Gortmaker > Cc: Peter Zijlstra > Cc: Ravi V. Shankar > Cc: Shuah Khan > Cc: Vlastimil Babka > Signed-off-by: Ricardo Neri > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/include/asm/disabled-features.h | 8 +++++++- > arch/x86/include/uapi/asm/processor-flags.h | 2 ++ > 3 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 5f0931b..81ef3bbe 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -282,6 +282,7 @@ > #define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ > > /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ > +#define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */ > #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ > #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ > > diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h > index 85599ad..4707445 100644 > --- a/arch/x86/include/asm/disabled-features.h > +++ b/arch/x86/include/asm/disabled-features.h > @@ -16,6 +16,12 @@ > # define DISABLE_MPX (1<<(X86_FEATURE_MPX & 31)) > #endif > > +#ifdef CONFIG_X86_INTEL_UMIP ^^^^^ What's this? Let's try to do this with a minimum of configuration.