Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932761AbcKHQZn (ORCPT ); Tue, 8 Nov 2016 11:25:43 -0500 Received: from mout.kundenserver.de ([212.227.126.133]:58413 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932582AbcKHQZk (ORCPT ); Tue, 8 Nov 2016 11:25:40 -0500 From: Arnd Bergmann To: "zhichang.yuan" Cc: catalin.marinas@arm.com, will.deacon@arm.com, robh+dt@kernel.org, bhelgaas@google.com, mark.rutland@arm.com, olof@lixom.net, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, linux-kernel@vger.kernel.org, linuxarm@huawei.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, minyard@acm.org, benh@kernel.crashing.org, liviu.dudau@arm.com, zourongrong@gmail.com, john.garry@huawei.com, gabriele.paoloni@huawei.com, zhichang.yuan02@gmail.com, kantyzc@163.com, xuwei5@hisilicon.com Subject: Re: [PATCH V5 3/3] ARM64 LPC: LPC driver implementation on Hip06 Date: Tue, 08 Nov 2016 17:24:35 +0100 Message-ID: <1555494.4IFvGxvsfe@wuerfel> User-Agent: KMail/5.1.3 (Linux/4.4.0-34-generic; KDE/5.18.0; x86_64; ; ) In-Reply-To: <1478576829-112707-4-git-send-email-yuanzhichang@hisilicon.com> References: <1478576829-112707-1-git-send-email-yuanzhichang@hisilicon.com> <1478576829-112707-4-git-send-email-yuanzhichang@hisilicon.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:qL/o3/XdH/c3xN7xypQCUWOUayyK+KqKiJkFolTUrzH4vHojINP gbBeTUurWYuTBL7UnKIAaAUi+HQp51I/vL2BMNJbC1MoSphDF/NTJ5mD8H4ocR+7eAb82wq 0eGeehPgeARyeX7/1Teb99WK1yY8Dy7Emn9NIuwjvckNyXIQ6lOC5ZJVGyu4FdX4SQDBHKI q3Q8IL5NwZqAGeHgBo2NA== X-UI-Out-Filterresults: notjunk:1;V01:K0:XAerCTwvDto=:0ZzIXKTXIJHrfAVD4CYH6d Ikph/n8weo05aLRGBXPYZkCXMucn8nN5oJoU+uq9i4u/eM3663LNW7PqcFESVNr1prn1O0LTy S+2qVIw05wzmKToq/funWclMp1zLIoBmCmK3plNM5xWs+dR6eB922G84Y/cuUXAWuDOeUj8MM j4HQKlR/oxa/YtQ28LRvTCVMguGeDiztZCsjeguV/C7HHKA6eb1gCtGxK9MDp5bbZbx2uO+r6 FZYpJCJdYh5wP/kbOrV9144b9vXEkYMFq//q99l31Ul+Y7v45wGIzm4rCqFdXZzoui6Bq7Pc6 n1xfniamU9mxYe6aaBPzTpQKcekynlNtQPlAh55TsRrivDteB6fdJgapvAp0mFdwGdt7JobSM LW9+UsflrmwZvPKC5dztjaOgCe+5/6+scl46C+uedSBZJTPbIkJ1aTVzETw3E034MxoWpVUZQ yjsQMQtqzEcUymTb1BzYDZAubCmN6AGkoo1QIkn/BiMxjI1fGMeH5oq2bBEIACt9TUD/U1fGi LfTuh/+/Iuh+sa2sQhIbrF6hSm634F/XbyOfbuXKEDFXDgJXO7WS78YBWhIXY5lnYxrXXuwP3 A89smlHaj/upovmMzWQMLzzn5+Z8ks2t1xBcBbr9aX8xX7Zz9qE4r92FL+5Fjwq3LHii6nNik oy0sLguiAyz+ymCsa87HLFyONbISSkvUor26QOO/80mevASsQ0bxP2ZXp/c6Zub+OZ5e+pJIy IPIEZ0hg3KIfVhb8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1014 Lines: 22 On Tuesday, November 8, 2016 11:47:09 AM CET zhichang.yuan wrote: > + /* > + * The first PCIBIOS_MIN_IO is reserved specifically for indirectIO. > + * It will separate indirectIO range from pci host bridge to > + * avoid the possible PIO conflict. > + * Set the indirectIO range directly here. > + */ > + lpcdev->io_ops.start = 0; > + lpcdev->io_ops.end = PCIBIOS_MIN_IO - 1; > + lpcdev->io_ops.devpara = lpcdev; > + lpcdev->io_ops.pfin = hisilpc_comm_in; > + lpcdev->io_ops.pfout = hisilpc_comm_out; > + lpcdev->io_ops.pfins = hisilpc_comm_ins; > + lpcdev->io_ops.pfouts = hisilpc_comm_outs; I have to look at patch 2 in more detail again, after missing a few review rounds. I'm still a bit skeptical about hardcoding a logical I/O port range here, and would hope that we can just go through the same assignment of logical port ranges that we have for PCI buses, decoupling the bus addresses from the linux-internal ones. Arnd