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From: Kyle Huey <me@kylehuey.com>
Date: Tue, 8 Nov 2016 11:38:25 -0800
Message-ID: <CAP045ApgFPBVoQLKyC0t46Axy=fYF53ToNM2AK1ghCqbGRi6TQ@mail.gmail.com>
Subject: Re: [PATCH v10 5/7] x86/cpufeature: Detect CPUID faulting support
To: Thomas Gleixner <tglx@linutronix.de>
Cc: "Robert O'Callahan" <robert@ocallahan.org>,
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On Tue, Nov 8, 2016 at 11:06 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
> On Tue, 8 Nov 2016, Kyle Huey wrote:
>
>> Intel supports faulting on the CPUID instruction beginning with Ivy Bridge.
>> When enabled, the processor will fault on attempts to execute the CPUID
>> instruction with CPL>0. This will allow a ptracer to emulate the CPUID
>> instruction.
>>
>> Bit 31 of MSR_PLATFORM_INFO advertises support for this feature. It is
>> documented in detail in Section 2.3.2 of
>> http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/virtualization-technology-flexmigration-application-note.pdf

Done. https://bugzilla.kernel.org/attachment.cgi?id=243991

> Can you please stick that document into the kernel bugzilla, as it's going
> to be on a different place before this gets merged into Linus tree?
>
> See: http://lkml.kernel.org/r/1478631281-5061-1-git-send-email-kan.liang@intel.com
>
>> +     static const struct msr_bit msr_bits[] = {
>> +             { X86_FEATURE_CPUID_FAULT,      MSR_PLATFORM_INFO, 31 },
>
> Can you please make that PLATINFO_CPUID_FAULT_BIT instead of 31?

Sure.

- Kyle