Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753032AbcKHXOl (ORCPT ); Tue, 8 Nov 2016 18:14:41 -0500 Received: from gate.crashing.org ([63.228.1.57]:56414 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751671AbcKHXOj (ORCPT ); Tue, 8 Nov 2016 18:14:39 -0500 Message-ID: <1478646779.7430.66.camel@kernel.crashing.org> Subject: Re: [PATCH V5 2/3] ARM64 LPC: Add missing range exception for special ISA From: Benjamin Herrenschmidt To: Mark Rutland , "zhichang.yuan" Cc: catalin.marinas@arm.com, will.deacon@arm.com, robh+dt@kernel.org, bhelgaas@google.com, olof@lixom.net, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, linux-kernel@vger.kernel.org, linuxarm@huawei.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, minyard@acm.org, liviu.dudau@arm.com, zourongrong@gmail.com, john.garry@huawei.com, gabriele.paoloni@huawei.com, zhichang.yuan02@gmail.com, kantyzc@163.com, xuwei5@hisilicon.com, marc.zyngier@arm.com Date: Wed, 09 Nov 2016 10:12:59 +1100 In-Reply-To: <20161108114953.GB15297@leverpostej> References: <1478576829-112707-1-git-send-email-yuanzhichang@hisilicon.com> <1478576829-112707-3-git-send-email-yuanzhichang@hisilicon.com> <20161108114953.GB15297@leverpostej> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.20.5 (3.20.5-1.fc24) Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1091 Lines: 28 On Tue, 2016-11-08 at 11:49 +0000, Mark Rutland wrote: > > My understanding of ISA (which may be flawed) is that it's not part of > the PCI host bridge, but rather on x86 it happens to share the IO space > with PCI. Sort-of. On some systems it actually goes through PCI and there's a PCI->ISA bridge that uses substractive decoding to the legacy devices. > So, how about this becomes: > >   Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which >   provides access to some legacy ISA devices. > > I believe that we could theoretically have multiple independent LPC/ISA > busses, as is possible with PCI on !x86 systems. If the current ISA code > assumes a singleton bus, I think that's something that needs to be fixed > up more generically. > > I don't see why we should need any architecture-specific code here. Why > can we not fix up the ISA bus code in drivers/of/address.c such that it > handles multiple ISA bus instances, and translates all sub-device > addresses relative to the specific bus instance? What in that code prevents that today ? Cheers, Ben.