Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933357AbcKINYR (ORCPT ); Wed, 9 Nov 2016 08:24:17 -0500 Received: from mail-pf0-f195.google.com ([209.85.192.195]:36081 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932533AbcKINXe (ORCPT ); Wed, 9 Nov 2016 08:23:34 -0500 From: Caesar Wang To: Heiko Stuebner Cc: eddie.cai@rock-chips.com, tfiga@chromium.org, Brian Norris , Caesar Wang , Douglas Anderson , David Wu , Jianqun Xu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, zhangqing , Shawn Lin , Rob Herring , Will Deacon , linux-rockchip@lists.infradead.org, Mark Rutland , Catalin Marinas , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 8/9] arm64: dts: rockchip: support dwc3 USB for rk3399 Date: Wed, 9 Nov 2016 21:22:00 +0800 Message-Id: <1478697721-2323-9-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1478697721-2323-1-git-send-email-wxt@rock-chips.com> References: <1478697721-2323-1-git-send-email-wxt@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2439 Lines: 82 From: Brian Norris Add the dwc3 usb needed node information for rk3399. Signed-off-by: Brian Norris Signed-off-by: Caesar Wang --- Changes in v2: - the original patches from brian posting on https://chromium-review.googlesource.com/343603 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 54 ++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 09ebf4e..3659c56 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -353,6 +353,60 @@ status = "disabled"; }; + usbdrd3_0: usb@fe800000 { + compatible = "rockchip,rk3399-dwc3"; + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "grf_clk"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + usbdrd_dwc3_0: dwc3@fe800000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe800000 0x0 0x100000>; + interrupts = ; + dr_mode = "otg"; + phys = <&tcphy0_usb3>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,xhci-slow-suspend-quirk; + status = "disabled"; + }; + }; + + usbdrd3_1: usb@fe900000 { + compatible = "rockchip,rk3399-dwc3"; + clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, + <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "grf_clk"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + usbdrd_dwc3_1: dwc3@fe900000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe900000 0x0 0x100000>; + interrupts = ; + dr_mode = "host"; + phys = <&tcphy1_usb3>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,xhci-slow-suspend-quirk; + status = "disabled"; + }; + }; + gic: interrupt-controller@fee00000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; -- 2.7.4