Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933374AbcKINZC (ORCPT ); Wed, 9 Nov 2016 08:25:02 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:35900 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932797AbcKINWn (ORCPT ); Wed, 9 Nov 2016 08:22:43 -0500 From: Caesar Wang To: Heiko Stuebner Cc: eddie.cai@rock-chips.com, tfiga@chromium.org, Mark Yao , Yakir Yang , Caesar Wang , Douglas Anderson , David Wu , Jianqun Xu , devicetree@vger.kernel.org, Brian Norris , linux-kernel@vger.kernel.org, zhangqing , linux-rockchip@lists.infradead.org, Rob Herring , Will Deacon , Ziyuan Xu , Mark Rutland , Catalin Marinas , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/9] arm64: dts: rockchip: add VOP and VOP iommu node for rk3399 Date: Wed, 9 Nov 2016 21:21:55 +0800 Message-Id: <1478697721-2323-4-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1478697721-2323-1-git-send-email-wxt@rock-chips.com> References: <1478697721-2323-1-git-send-email-wxt@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2464 Lines: 86 From: Mark Yao Add the core display-subsystem node and the two display controllers available on the rk3399. Signed-off-by: Mark Yao Signed-off-by: Yakir Yang Signed-off-by: Caesar Wang --- Changes in v2: None arch/arm64/boot/dts/rockchip/rk3399.dtsi | 58 ++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index e5b5b3d..f1d289a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1290,6 +1290,64 @@ status = "disabled"; }; + vopl: vop@ff8f0000 { + compatible = "rockchip,rk3399-vop-lit"; + reg = <0x0 0xff8f0000 0x0 0x3efc>; + interrupts = ; + clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vopl_mmu>; + status = "disabled"; + + vopl_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + vopl_mmu: iommu@ff8f3f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff8f3f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vopl_mmu"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vopb: vop@ff900000 { + compatible = "rockchip,rk3399-vop-big"; + reg = <0x0 0xff900000 0x0 0x3efc>; + interrupts = ; + clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vopb_mmu>; + status = "disabled"; + + vopb_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + vopb_mmu: iommu@ff903f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff903f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vopb_mmu"; + #iommu-cells = <0>; + status = "disabled"; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vopl_out>, <&vopb_out>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3399-pinctrl"; rockchip,grf = <&grf>; -- 2.7.4