Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754627AbcKIRU2 (ORCPT ); Wed, 9 Nov 2016 12:20:28 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:36816 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752429AbcKIRU0 (ORCPT ); Wed, 9 Nov 2016 12:20:26 -0500 Subject: Re: [PATCH v15 4/4] arm: dts: mt2701: Use real clock for UARTs To: Erin Lo , Mike Turquette , Stephen Boyd , Rob Herring References: <1478245388-1412-1-git-send-email-erin.lo@mediatek.com> <1478245388-1412-5-git-send-email-erin.lo@mediatek.com> Cc: Arnd Bergmann , Sascha Hauer , Daniel Kurtz , Philipp Zabel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, srv_heupstream@mediatek.com, ms.chen@mediatek.com, robert.chou@mediatek.com From: Matthias Brugger Message-ID: Date: Wed, 9 Nov 2016 18:20:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <1478245388-1412-5-git-send-email-erin.lo@mediatek.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2108 Lines: 73 On 11/04/2016 08:43 AM, Erin Lo wrote: > We used to use a fixed rate clock for the UARTs. Now that we have clock > support we can associate the correct clocks to the UARTs and drop the > 26MHz fixed rate UART clock. > > Signed-off-by: Erin Lo Applied, thanks. > --- > arch/arm/boot/dts/mt2701.dtsi | 18 ++++++++---------- > 1 file changed, 8 insertions(+), 10 deletions(-) > > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi > index c9a8dbf..7eab6f4 100644 > --- a/arch/arm/boot/dts/mt2701.dtsi > +++ b/arch/arm/boot/dts/mt2701.dtsi > @@ -73,12 +73,6 @@ > #clock-cells = <0>; > }; > > - uart_clk: dummy26m { > - compatible = "fixed-clock"; > - clock-frequency = <26000000>; > - #clock-cells = <0>; > - }; > - > clk26m: oscillator@0 { > compatible = "fixed-clock"; > #clock-cells = <0>; > @@ -186,7 +180,8 @@ > "mediatek,mt6577-uart"; > reg = <0 0x11002000 0 0x400>; > interrupts = ; > - clocks = <&uart_clk>; > + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; > + clock-names = "baud", "bus"; > status = "disabled"; > }; > > @@ -195,7 +190,8 @@ > "mediatek,mt6577-uart"; > reg = <0 0x11003000 0 0x400>; > interrupts = ; > - clocks = <&uart_clk>; > + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; > + clock-names = "baud", "bus"; > status = "disabled"; > }; > > @@ -204,7 +200,8 @@ > "mediatek,mt6577-uart"; > reg = <0 0x11004000 0 0x400>; > interrupts = ; > - clocks = <&uart_clk>; > + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; > + clock-names = "baud", "bus"; > status = "disabled"; > }; > > @@ -213,7 +210,8 @@ > "mediatek,mt6577-uart"; > reg = <0 0x11005000 0 0x400>; > interrupts = ; > - clocks = <&uart_clk>; > + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; > + clock-names = "baud", "bus"; > status = "disabled"; > }; > }; >