Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754450AbcKIVMr (ORCPT ); Wed, 9 Nov 2016 16:12:47 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:59280 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750917AbcKIVMp (ORCPT ); Wed, 9 Nov 2016 16:12:45 -0500 Date: Wed, 9 Nov 2016 22:09:38 +0100 (CET) From: Thomas Gleixner To: Bin Gao cc: Ingo Molnar , H Peter Anvin , x86@kernel.org, Peter Zijlstra , linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag In-Reply-To: <1478020482-231459-2-git-send-email-bin.gao@intel.com> Message-ID: References: <1478020482-231459-1-git-send-email-bin.gao@intel.com> <1478020482-231459-2-git-send-email-bin.gao@intel.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2890 Lines: 66 On Tue, 1 Nov 2016, Bin Gao wrote: > The X86_FEATURE_TSC_RELIABLE flag in Linux kernel implies both reliable > (at runtime) and trustable (at calibration). But reliable running and > trustable calibration are logically irrelevant. Per Thomas Gleixner's > suggestion we would like to split this flag into two separate flags: > X86_FEATURE_TSC_RELIABLE - running reliably > X86_FEATURE_TSC_KNOWN_FREQ - frequency is known (no calibration required) > These two flags allow Linux kernel to act differently based on > processor/SoC's capability, i.e. no watchdog on TSC if TSC is reliable, > and no calibration if TSC frequency is known. > > Current Linux kernel already gurantees calibration is skipped for > processors that can report TSC frequency by CPUID or MSR. However, the > delayed calibration is still not skipped for these CPUID/MSR capable > processors. The new flag X86_FEATURE_TSC_KNOWN_FREQ added by this patch > will gurantee the delayed calibration is skipped. > > Signed-off-by: Bin Gao > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/kernel/tsc.c | 6 +++--- > 2 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index a396292..7f6a5f8 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -106,6 +106,7 @@ > #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ > #define X86_FEATURE_EAGER_FPU ( 3*32+29) /* "eagerfpu" Non lazy FPU restore */ > #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ > +#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ > > /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ > #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ > diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c > index 46b2f41..b4c82f8 100644 > --- a/arch/x86/kernel/tsc.c > +++ b/arch/x86/kernel/tsc.c > @@ -1283,10 +1283,10 @@ static int __init init_tsc_clocksource(void) > clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; > > /* > - * Trust the results of the earlier calibration on systems > - * exporting a reliable TSC. > + * When TSC frequency is known (generally got by MSR or CPUID), we skip > + * the refined calibration and directly register it as a clocksource. > */ > - if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) { > + if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { This causes a regression, because with only this patch applied the architectures which use the reliable flag for this today are not longer taking this path. The proper thing to do here is to make this: if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE) || boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { and remove the RELIABLE flag ckeck after the existing users are converted. Thanks, tglx