Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932398AbcKJAyM (ORCPT ); Wed, 9 Nov 2016 19:54:12 -0500 Received: from mail-cys01nam02on0069.outbound.protection.outlook.com ([104.47.37.69]:36634 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752933AbcKJAyG (ORCPT ); Wed, 9 Nov 2016 19:54:06 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Thomas.Lendacky@amd.com; From: Tom Lendacky Subject: [RFC PATCH v3 20/20] x86: Add support to make use of Secure Memory Encryption To: , , , , , , , , CC: Rik van Riel , Radim =?utf-8?b?S3LEjW3DocWZ?= , Arnd Bergmann , Jonathan Corbet , Matt Fleming , Joerg Roedel , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Larry Woodman , "Ingo Molnar" , Borislav Petkov , Andy Lutomirski , "H. Peter Anvin" , Andrey Ryabinin , Alexander Potapenko , "Thomas Gleixner" , Dmitry Vyukov Date: Wed, 9 Nov 2016 18:38:38 -0600 Message-ID: <20161110003838.3280.23327.stgit@tlendack-t1.amdoffice.net> In-Reply-To: <20161110003426.3280.2999.stgit@tlendack-t1.amdoffice.net> References: <20161110003426.3280.2999.stgit@tlendack-t1.amdoffice.net> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: DM5PR20CA0010.namprd20.prod.outlook.com (10.173.136.148) To BN6PR12MB1138.namprd12.prod.outlook.com (10.168.226.140) X-MS-Office365-Filtering-Correlation-Id: 96277412-891d-419e-4231-08d40901ec89 X-Microsoft-Exchange-Diagnostics: 1;BN6PR12MB1138;2:gLQ5rLr5R976njzrfmBUOfBg+LSn10EDAzALrocAg4Hu0MjffrV3/LqioCPyU/cqH1h2kI6MUYu4NRgRjJtuz6hTlvBIERlE6pLEEvwQh54ZyujFXO/UtOKsfbLpFLx8AhHc4seA2Y/YAMNPaUuweU6QFO0IMwavyMhdeoVRdfjBDLuGRY0hRn9gEqtz08tSEEH7CKg6jVPTFlmnhFLFZQ==;3:21tLhY1PjPCLsJayTTa3zYKyeOeAFYV0Fte13hg0Lift7rPCtv8/IplYwPGXk5gKsyL3ezRAyjSImpBqjjyII5VIUJJj0ijO9mpKFxh0Rx5Z+Ffun48hdcyyoGtSy0l4XmXftWAduZ7qDJmrsjuq/g==;25:ytRS6anfLhJD+L7mhPsPhQ44mRzDRBrVmIXWy8K9ZssKZdeHhk9nTc5wqLMLZ/IiPu0dsfMqsLFKjCGKcoPxhZEjoWNIDEFlCm0kIHVtwSp6kX4XLCXEbIzjNJXrbCq4xvPvO8566iETa2u10cAcI0psWuaeqsIef6gQ2kWoa+pnPW3wQYUiAty/pRrH44jEHioy/zHxkHRu2zKJ2adXCA0/UaxTXqSdd5Kmpt0U1uOznv/nGtig0yX1pBNF78mq7BnWZin4SBnqA00UWCb36ULhaYLnwZAVajGjZ9kSFPcB2B18iYXbhkJ5ynWm64/yC0dL9r+DHKbKyAN2TGasy36HCi1qhJxJv5ciPiwjMDY7PE8J5xFsYkvKjzRyXEWfnoiLECajxS6x6DKZ63gXg+jZk8D6l2b5SX5521VFyfDmmBHkH+Q+xBKymSJpP6BI X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN6PR12MB1138; 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If both of these conditions are true, then the encryption mask is set and the kernel is encrypted "in place." Signed-off-by: Tom Lendacky --- arch/x86/kernel/head_64.S | 1 + arch/x86/kernel/mem_encrypt_init.c | 60 +++++++++++++++++++++++++++++++++++- arch/x86/mm/mem_encrypt.c | 2 + 3 files changed, 62 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index e8a7272..c225433 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -100,6 +100,7 @@ startup_64: * to include it in the page table fixups. */ push %rsi + movq %rsi, %rdi call sme_enable pop %rsi movq %rax, %r12 diff --git a/arch/x86/kernel/mem_encrypt_init.c b/arch/x86/kernel/mem_encrypt_init.c index 7bdd159..c94ceb8 100644 --- a/arch/x86/kernel/mem_encrypt_init.c +++ b/arch/x86/kernel/mem_encrypt_init.c @@ -16,9 +16,14 @@ #include #include +#include +#include +#include #ifdef CONFIG_AMD_MEM_ENCRYPT +static char sme_cmdline_arg[] __initdata = "mem_encrypt=on"; + extern void sme_encrypt_execute(unsigned long, unsigned long, unsigned long, void *, pgd_t *); @@ -219,7 +224,60 @@ unsigned long __init sme_get_me_mask(void) return sme_me_mask; } -unsigned long __init sme_enable(void) +unsigned long __init sme_enable(void *boot_data) { +#ifdef CONFIG_AMD_MEM_ENCRYPT + struct boot_params *bp = boot_data; + unsigned int eax, ebx, ecx, edx; + u64 msr; + unsigned long cmdline_ptr; + void *cmdline_arg; + + /* Check for an AMD processor */ + eax = 0; + ecx = 0; + native_cpuid(&eax, &ebx, &ecx, &edx); + if ((ebx != 0x68747541) || (edx != 0x69746e65) || (ecx != 0x444d4163)) + goto out; + + /* Check for the SME support leaf */ + eax = 0x80000000; + ecx = 0; + native_cpuid(&eax, &ebx, &ecx, &edx); + if (eax < 0x8000001f) + goto out; + + /* + * Check for the SME feature: + * CPUID Fn8000_001F[EAX] - Bit 0 + * Secure Memory Encryption support + * CPUID Fn8000_001F[EBX] - Bits 5:0 + * Pagetable bit position used to indicate encryption + */ + eax = 0x8000001f; + ecx = 0; + native_cpuid(&eax, &ebx, &ecx, &edx); + if (!(eax & 1)) + goto out; + + /* Check if SME is enabled */ + msr = native_read_msr(MSR_K8_SYSCFG); + if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT)) + goto out; + + /* + * Fixups have not been to applied phys_base yet, so we must obtain + * the address to the SME command line option in the following way. + */ + asm ("lea sme_cmdline_arg(%%rip), %0" + : "=r" (cmdline_arg) + : "p" (sme_cmdline_arg)); + cmdline_ptr = bp->hdr.cmd_line_ptr | ((u64)bp->ext_cmd_line_ptr << 32); + if (cmdline_find_option_bool((char *)cmdline_ptr, cmdline_arg)) + sme_me_mask = 1UL << (ebx & 0x3f); + +out: +#endif /* CONFIG_AMD_MEM_ENCRYPT */ + return sme_me_mask; } diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index e351003..d0bc3f5 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -251,6 +251,8 @@ void __init mem_encrypt_init(void) /* Make SWIOTLB use an unencrypted DMA area */ swiotlb_clear_encryption(); + + pr_info("AMD Secure Memory Encryption active\n"); } void swiotlb_set_mem_unenc(void *vaddr, unsigned long size)