Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964896AbcKJQwx (ORCPT ); Thu, 10 Nov 2016 11:52:53 -0500 Received: from mail-out.m-online.net ([212.18.0.10]:39075 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935238AbcKJQwu (ORCPT ); Thu, 10 Nov 2016 11:52:50 -0500 X-Auth-Info: Q5EHwuFPP17wX7rgbdVKP81y+tCZkhmvXgEx7yVvYfM= Subject: Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs To: Joel Holdsworth , Moritz Fischer References: <1478486962-26794-1-git-send-email-joel@airwebreathe.org.uk> <1478486962-26794-3-git-send-email-joel@airwebreathe.org.uk> <2255968d-b97c-2b9c-4e4d-7f3717a748e3@denx.de> <01d1a97b-2f43-49a6-51fb-e223ef4dce9b@airwebreathe.org.uk> <4bdba358-db18-48f1-3286-a7a7f4c30215@denx.de> <5828eb84-ab29-49e2-34f0-3cd7e527ca66@airwebreathe.org.uk> Cc: Alan Tull , Geert Uytterhoeven , Rob Herring , Devicetree List , Linux Kernel Mailing List , linux-spi@vger.kernel.org, Clifford Wolf From: Marek Vasut Message-ID: Date: Thu, 10 Nov 2016 13:11:08 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Icedove/45.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1709 Lines: 45 On 11/09/2016 07:54 PM, Joel Holdsworth wrote: > On 09/11/16 11:39, Marek Vasut wrote: >> On 11/09/2016 07:37 PM, Joel Holdsworth wrote: >>> On 09/11/16 05:01, Marek Vasut wrote: >>>> On 11/08/2016 06:30 PM, Joel Holdsworth wrote: >>>>>>>> On the whole, I don't think the zero-length transfers are too >>>>>>>> egregiously bad, and all the alternatives seem worse to me. >>>>>>> >>>>>>> So why not turn the CS line into GPIO and just toggle the GPIO? >>>>>> >>>>>> Does that work with *all* SPI controllers? >>>>>> >>>>> >>>>> It does not - no. See my other email. >>>> >>>> And is that line an actual CS of that lattice chip or a generic input >>>> which almost works like CS? >>>> >>> >>> I mean a generic output vs. a special CS output built into the SPI >>> master of the application processor. Take a look at how spi_set_cs(..) >>> works: >> >> No. I am asking whether the signal which is INPUT on the iCE40 side is >> really a chipselect signal for the SPI bus OR something which mostly >> behaves/looks like a chipselect but is not really a chipselect. > > Oh I see. The SS_B line is the SPI SlaveSelect for the configuration port. > > This is the text from the datasheet: > > "SPI Slave Select. Active Low. Includes an internal weak pull-up > resistor to VCC_SPI during configuration. During configuration, the > logic level sampled on this pin deter-mines the configuration mode used > by the iCE40 device. An input when sampled at the start of > configuration. An input when in SPI Peripheral configuration mode > (SPI_SS_B = Low). An output when in Master SPI Flash configuration mode." > > So yes - it is a "real" SPI chip-select line. OK, thanks for checking. -- Best regards, Marek Vasut