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In-Reply-To: <20161111100558.14629-2-wens@csie.org>
References: <20161111100558.14629-1-wens@csie.org> <20161111100558.14629-2-wens@csie.org>
From: Code Kipper <codekipper@gmail.com>
Date: Fri, 11 Nov 2016 11:10:44 +0100
Message-ID: <CAEKpxBkseMg2JvP7rrm2qFSCTsn60JyzoWFNFDrWNFDHkMuQtg@mail.gmail.com>
Subject: Re: [linux-sunxi] [PATCH] clk: sunxi-ng: sun8i-h3: Set
 CLK_SET_RATE_PARENT for audio module clocks
To: Chen-Yu Tsai <wens@csie.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@codeaurora.org>,
        Maxime Ripard <maxime.ripard@free-electrons.com>,
        linux-clk@vger.kernel.org,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        linux-kernel@vger.kernel.org,
        linux-sunxi <linux-sunxi@googlegroups.com>
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Sender: linux-kernel-owner@vger.kernel.org
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On 11 November 2016 at 11:05, Chen-Yu Tsai <wens@csie.org> wrote:
> The audio module clocks are supposed to be set according to the sample
> rate of the audio stream. The audio PLL provides the clock signal for
> thees module clocks, and only it is freely tunable.
nick! these
CK
>
> Set CLK_SET_RATE_PARENT for the audio module clocks so their users can
> properly tune the clock rate.
>
> Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> index 4d70590f05e3..21c427d86f28 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> @@ -394,16 +394,16 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
>  static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
>                                             "pll-audio-2x", "pll-audio" };
>  static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
> -                              0x0b0, 16, 2, BIT(31), 0);
> +                              0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
>
>  static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
> -                              0x0b4, 16, 2, BIT(31), 0);
> +                              0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
>
>  static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
> -                              0x0b8, 16, 2, BIT(31), 0);
> +                              0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
>
>  static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
> -                            0x0c0, 0, 4, BIT(31), 0);
> +                            0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
>
>  static SUNXI_CCU_GATE(usb_phy0_clk,    "usb-phy0",     "osc24M",
>                       0x0cc, BIT(8), 0);
> @@ -466,7 +466,7 @@ static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
>                              0x13c, 16, 3, BIT(31), 0);
>
>  static SUNXI_CCU_GATE(ac_dig_clk,      "ac-dig",       "pll-audio",
> -                     0x140, BIT(31), 0);
> +                     0x140, BIT(31), CLK_SET_RATE_PARENT);
>  static SUNXI_CCU_GATE(avs_clk,         "avs",          "osc24M",
>                       0x144, BIT(31), 0);
>
> --
> 2.10.2
>
> --
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