Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S938606AbcKLAEk (ORCPT ); Fri, 11 Nov 2016 19:04:40 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:42330 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936234AbcKLAEi (ORCPT ); Fri, 11 Nov 2016 19:04:38 -0500 DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 669E261545 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=sboyd@codeaurora.org Date: Fri, 11 Nov 2016 16:04:36 -0800 From: Stephen Boyd To: Jiancheng Xue Cc: mturquette@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, bin.chen@linaro.org, elder@linaro.org, hermit.wangheming@hisilicon.com, yanhaifeng@hisilicon.com, wenpan@hisilicon.com, howell.yang@hisilicon.com Subject: Re: [PATCH 1/2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC Message-ID: <20161112000436.GF5177@codeaurora.org> References: <1477721618-10809-1-git-send-email-xuejiancheng@hisilicon.com> <1477721618-10809-2-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1477721618-10809-2-git-send-email-xuejiancheng@hisilicon.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 451 Lines: 14 On 10/29, Jiancheng Xue wrote: > Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset > Generator) module generates clock and reset signals used > by other module blocks on SoC. > > Signed-off-by: Jiancheng Xue > Acked-by: Rob Herring > --- Applied to clk-hisi and merged into clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project