Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751562AbcKNBYj (ORCPT ); Sun, 13 Nov 2016 20:24:39 -0500 Received: from szxga03-in.huawei.com ([119.145.14.66]:31975 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751081AbcKNBYh (ORCPT ); Sun, 13 Nov 2016 20:24:37 -0500 Subject: Re: [PATCH 2/2] clk: hisilicon: add CRG driver for Hi3516CV300 SoC To: Stephen Boyd References: <1477721618-10809-1-git-send-email-xuejiancheng@hisilicon.com> <1477721618-10809-3-git-send-email-xuejiancheng@hisilicon.com> <20161112000415.GE5177@codeaurora.org> CC: , , , , , , , , , , , From: Jiancheng Xue Message-ID: <0c3b49a4-f58c-253a-fd87-ab52b0b26010@hisilicon.com> Date: Mon, 14 Nov 2016 09:24:17 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <20161112000415.GE5177@codeaurora.org> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.245.243] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 654 Lines: 23 Hi Stephen, On 2016/11/12 8:04, Stephen Boyd wrote: > On 10/29, Jiancheng Xue wrote: > > Should be a From: Pan Wen here? > >> Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset >> Generator) module generates clock and reset signals used >> by other module blocks on SoC. >> >> Signed-off-by: Pan Wen > > And you should have signed it off? Care to resend or state that > this is incorrectly attributed to you instead of Pan Wen? > Pan Wen is the main author of this patch. I just made some small modification with agreement from him. Do I need to resend this patch if it's better to add my signed-off? Thanks, Jiancheng