Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935450AbcKNSPe (ORCPT ); Mon, 14 Nov 2016 13:15:34 -0500 Received: from mail-wm0-f51.google.com ([74.125.82.51]:36700 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932899AbcKNSPc (ORCPT ); Mon, 14 Nov 2016 13:15:32 -0500 MIME-Version: 1.0 In-Reply-To: <1479106911-16049-2-git-send-email-wulf@rock-chips.com> References: <1479106911-16049-1-git-send-email-wulf@rock-chips.com> <1479106911-16049-2-git-send-email-wulf@rock-chips.com> From: Doug Anderson Date: Mon, 14 Nov 2016 10:15:30 -0800 Message-ID: Subject: Re: [PATCH v2 1/2] phy: rockchip-inno-usb2: correct clk_ops callback To: William Wu Cc: Kishon Vijay Abraham I , =?UTF-8?Q?Heiko_St=C3=BCbner?= , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "open list:ARM/Rockchip SoC..." , "devicetree@vger.kernel.org" , Rob Herring , Frank Wang , =?UTF-8?B?6buE5rab?= , Brian Norris , Guenter Roeck Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 741 Lines: 18 William On Sun, Nov 13, 2016 at 11:01 PM, William Wu wrote: > Since we needs to delay ~1ms to wait for 480MHz output clock > of USB2 PHY to become stable after turn on it, the delay time > is pretty long for something that's supposed to be "atomic" > like a clk_enable(). Consider that clk_enable() will disable > interrupt and that a 1ms interrupt latency is not sensible. > > The 480MHz output clock should be handled in prepare callbacks > which support gate a clk if the operation may sleep. > > Signed-off-by: William Wu > --- > drivers/phy/phy-rockchip-inno-usb2.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) Reviewed-by: Douglas Anderson