Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933914AbcKPTlE (ORCPT ); Wed, 16 Nov 2016 14:41:04 -0500 Received: from mail-qk0-f175.google.com ([209.85.220.175]:33905 "EHLO mail-qk0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932219AbcKPTlC (ORCPT ); Wed, 16 Nov 2016 14:41:02 -0500 MIME-Version: 1.0 In-Reply-To: <582AF350.1000007@nvidia.com> References: <1478089037-26441-1-git-send-email-ldewangan@nvidia.com> <5825B6D4.1000600@nvidia.com> <582AF350.1000007@nvidia.com> From: Linus Walleij Date: Wed, 16 Nov 2016 20:41:01 +0100 Message-ID: Subject: Re: [PATCH 1/1] gpio: lib: Add gpio_is_enabled() to get pin mode To: Laxman Dewangan Cc: Alexandre Courbot , Arnd Bergmann , "linux-gpio@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arch@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1036 Lines: 23 On Tue, Nov 15, 2016 at 12:36 PM, Laxman Dewangan wrote: > [Me] >> It would be more natural to add a function pinctrl_is_gpio(unsigned gpio) >> to call back to the pin controller, then that can be called from >> the generic or driver-specific debug print callback. > > > We have two type of IPs, GPIO mode is configured in the register which is > part of GPIO controller and in other IP, it is configured in register which > is in pincontroller registers. > > Your suggested API pinctrl_is_gpio() will definitely help on second case and > I will work on this once we will have the new IP driver in mainline. This > will be in coming T186 patches. I don't really understand this. In both cases we are dealing with pin muxing and that belongs in the pin control subsystem. What register range the stuff is in and whether it is called "GPIO block" in the datasheet does not concern me, it is a pin controller from the point of the view of the kernel subsystems, if it can multiplex pads/pins. Yours, Linus Walleij