Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1946032AbcKQLue (ORCPT ); Thu, 17 Nov 2016 06:50:34 -0500 Received: from mail-sn1nam02on0088.outbound.protection.outlook.com ([104.47.36.88]:6320 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1422650AbcKQLuc (ORCPT ); Thu, 17 Nov 2016 06:50:32 -0500 From: Rafal Ozieblo To: "harini.katakam@xilinx.com" CC: "nicolas.ferre@atmel.com" , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [RFC PATCH 2/2] net: macb: Add 64 bit addressing support for GEM Thread-Topic: Re: [RFC PATCH 2/2] net: macb: Add 64 bit addressing support for GEM Thread-Index: AdJAwW8MJ5HTUf0CQJuSGAEObl6kgw== Date: Thu, 17 Nov 2016 11:50:28 +0000 Message-ID: Reply-To: Rafal Ozieblo Accept-Language: pl-PL, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=rafalo@cadence.com; x-originating-ip: [213.131.238.28] x-microsoft-exchange-diagnostics: 1;BN3PR07MB2515;7:yKF43yeqHCY/VKrMVoWViYJdQB5GcmFTzm06bepnq7PKJG3UIe8GKlX6cC6j+Q+eUezyt+sEPqy5wl0ZPAH+/5/J3HIiMtGV8wM0clVljz5bY9v89I1nrOb6NpvpRwKZPz3Z7OpeD4x44XSng815JLRtXjX9DQt8950OvOli9105Ne4Sx7cpdscluqZu23mpi8769ghZ+IPQVnFQyC9c8Cw/kJVuOOtR9hHlGobYGKFYULbUnREzCo0bfCrKfK/vXadMc6c3xKO9TzhllJSjlzWQb+NjUbFiFQ1qRQG226jH/PAmclCd9od/Bc0aFD/LJneR7eyt0V6FuMSAMXy0lLP5H4o7j7arg5PqhtV8QBQ=;20:LnJ2ogbUkwsC7zTyWssQC0ldsd9cBO2JH4teUDSMytJilwOOIjXSqtXOuCRzeESygAfyIJQm1VnaRXYdBw/R3etFNXmj7aYVJV5GSCFgg6OvDMPfywr2YzoQkx7M6UGj+/ZO+zhdqx77fP3Ta7PutWqAxIRjBtt61ruJwSNJ5yywlXTF6lnzXT6pFrRQrT08eV4zTRpieo4Dru+4Ff5sZKos3ioF/AjyKiA4cNt0SYsIYe7U2hCf80EOzvZSbQyS x-ms-office365-filtering-correlation-id: d58fa72a-06f2-4df6-9a3f-08d40edfed6c x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001);SRVR:BN3PR07MB2515; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6060326)(6040281)(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046)(6041223)(6061324);SRVR:BN3PR07MB2515;BCL:0;PCL:0;RULEID:;SRVR:BN3PR07MB2515; x-forefront-prvs: 01294F875B x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(7916002)(199003)(36092001)(189002)(2351001)(2501003)(50986999)(99286002)(8676002)(77096005)(106356001)(5660300001)(189998001)(3846002)(81166006)(86362001)(105586002)(7846002)(9686002)(2900100001)(8666005)(6116002)(6506003)(8936002)(7736002)(101416001)(305945005)(81156014)(4326007)(102836003)(2906002)(54356999)(43066003)(53806999)(74316002)(3660700001)(97736004)(33656002)(68736007)(87936001)(66066001)(6916009)(5640700001)(229853002)(122556002)(3280700002)(3450700001)(110136003)(7696004)(76576001)(7059030)(217873001);DIR:OUT;SFP:1101;SCL:1;SRVR:BN3PR07MB2515;H:BN3PR07MB2516.namprd07.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;A:1;MX:1;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" MIME-Version: 1.0 X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Nov 2016 11:50:28.6733 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR07MB2515 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id uAHBohtr010695 Content-Length: 994 Lines: 36 Hello, I think, there could a bug in your patch. > + > +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT > + dmacfg |= GEM_BIT(ADDR64); > +#endif You enable 64 bit addressing (64b dma bus width) always when appropriate architecture config option is enabled. But there are some legacy controllers which do not support that feature. According Cadence hardware team: "64 bit addressing was added in July 2013. Earlier version do not have it. This feature was enhanced in release August 2014 to have separate upper address values for transmit and receive." > /* Bitfields in NSR */ > @@ -474,6 +479,10 @@ > struct macb_dma_desc { > u32 addr; > u32 ctrl; > +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT > + u32 addrh; > + u32 resvd; > +#endif > }; It will not work for legacy hardware. Old descriptor is 2 words wide, the new one is 4 words wide. If you enable CONFIG_ARCH_DMA_ADDR_T_64BIT but hardware doesn't support it at all, you will miss every second descriptor. Regards, Rafal ?