Date: Fri, 9 May 2003 04:24:17 +0200
From: Andi Kleen <ak@suse.de>
To: paubert <paubert@iram.es>
Cc: linux-kernel@vger.kernel.org, Linus Torvalds <torvalds@transmeta.com>,
       Andi Kleen <ak@suse.de>, David Mosberger <davidm@hpl.hp.com>
Subject: Re: [PATCH] Mask mxcsr according to cpu features.
Message-ID: <20030509022417.GB15829@Wotan.suse.de>
References: <20030509004200.A22795@mrt-lx16.iram.es>
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On Fri, May 09, 2003 at 12:42:01AM +0000, paubert wrote:
> 
> [CC'ed to x86_64 and ia64 maintainers because they might have the 
> same issues. For existing x86_64 processors, s/0xffbf/0xffff/ in 
> arch/x86-64/ia32/{fpu32,ptrace32}.c might be sufficient]
> 
> With SSE2, mxcsr bit 6 is defined as controlling whether
> denormals should be treated as zeroes or not. Setting it
> no more causes an exception, but with the current code it 
> would be cleared at every signal return which is a bit harsh.
> 
> The following patch fixes this (2.5, but easily ported to 2.4).

x86-64 does it in a different way. It just handles the 
possible exception on FXRSTOR with an __ex_table handler.
With that all the mxcsr masking can be dropped.

It was already this way for 64bit programs, but the 32bit emulation
still masks. I'm not sure I can change that - in theory it could
break existing programs.

-Andi
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