Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752335AbcKRAgC (ORCPT ); Thu, 17 Nov 2016 19:36:02 -0500 Received: from mga01.intel.com ([192.55.52.88]:51099 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751252AbcKRAgB (ORCPT ); Thu, 17 Nov 2016 19:36:01 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,655,1473145200"; d="scan'208";a="192784319" From: "Luck, Tony" To: Andi Kleen Cc: Tony Luck , linux-kernel@vger.kernel.org, Boris Petkov Subject: [PATCH 2/2] mcelog: Print the PPIN in machine check records when it is available Date: Thu, 17 Nov 2016 16:35:47 -0800 Message-Id: <1479429348-1664-1-git-send-email-tony.luck@intel.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1232 Lines: 41 From: Tony Luck Intel Xeons from Ivy Bridge onwards support a processor identification number. Kernels v4.9 and higher include it in the "mce" record. Signed-off-by: Tony Luck --- mcelog.c | 3 +++ mcelog.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/mcelog.c b/mcelog.c index 7214a0d23f65..e79996db9b5b 100644 --- a/mcelog.c +++ b/mcelog.c @@ -441,6 +441,9 @@ static void dump_mce(struct mce *m, unsigned recordlen) if (n > 0) Wprintf("\n"); + if (recordlen >= offsetof(struct mce, ppin) && m->ppin) + n += Wprintf("PPIN %llx\n", m->ppin); + if (recordlen >= offsetof(struct mce, cpuid) && m->cpuid) { u32 fam, mod; parse_cpuid(m->cpuid, &fam, &mod); diff --git a/mcelog.h b/mcelog.h index 254b3a092fba..9a54077e5474 100644 --- a/mcelog.h +++ b/mcelog.h @@ -31,6 +31,9 @@ struct mce { __u32 socketid; /* CPU socket ID */ __u32 apicid; /* CPU initial apic ID */ __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */ + __u64 synd; /* MCA_SYND MSR: only valid on SMCA systems */ + __u64 ipid; /* MCA_IPID MSR: only valid on SMCA systems */ + __u64 ppin; /* Protected Processor Inventory Number */ }; #define X86_VENDOR_INTEL 0 -- 2.7.4