Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753042AbcKRKHa (ORCPT ); Fri, 18 Nov 2016 05:07:30 -0500 Received: from terminus.zytor.com ([198.137.202.10]:53434 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752136AbcKRKH2 (ORCPT ); Fri, 18 Nov 2016 05:07:28 -0500 Date: Fri, 18 Nov 2016 02:05:57 -0800 From: tip-bot for Bin Gao Message-ID: Cc: tglx@linutronix.de, bin.gao@intel.com, hpa@zytor.com, linux-kernel@vger.kernel.org, peterz@infradead.org, bin.gao@linux.intel.com, mingo@kernel.org Reply-To: mingo@kernel.org, bin.gao@linux.intel.com, peterz@infradead.org, linux-kernel@vger.kernel.org, hpa@zytor.com, bin.gao@intel.com, tglx@linutronix.de In-Reply-To: <1479241644-234277-4-git-send-email-bin.gao@linux.intel.com> References: <1479241644-234277-4-git-send-email-bin.gao@linux.intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/timers] x86/tsc: Mark Intel ATOM_GOLDMONT TSC reliable Git-Commit-ID: 4635fdc696a8e89eead3ea1712ae6ada38538d40 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1640 Lines: 45 Commit-ID: 4635fdc696a8e89eead3ea1712ae6ada38538d40 Gitweb: http://git.kernel.org/tip/4635fdc696a8e89eead3ea1712ae6ada38538d40 Author: Bin Gao AuthorDate: Tue, 15 Nov 2016 12:27:23 -0800 Committer: Thomas Gleixner CommitDate: Fri, 18 Nov 2016 10:58:30 +0100 x86/tsc: Mark Intel ATOM_GOLDMONT TSC reliable On Intel GOLDMONT Atom SoC TSC is the only available clocksource, so there is no way to do software calibration or have a watchdog clocksource for it. Software calibration is already disabled via the TSC_KNOWN_FREQ flag, but the watchdog requirement still persists, so such systems cannot switch to high resolution/nohz mode. Mark it reliable, so it becomes usable. Hardware teams confirmed that this is safe on that SoC. Signed-off-by: Bin Gao Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/1479241644-234277-4-git-send-email-bin.gao@linux.intel.com Signed-off-by: Thomas Gleixner --- arch/x86/kernel/tsc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index e58c319..f4dfdaa 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -709,6 +709,13 @@ unsigned long native_calibrate_tsc(void) */ setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); + /* + * For Atom SoCs TSC is the only reliable clocksource. + * Mark TSC reliable so no watchdog on it. + */ + if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT) + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); + return crystal_khz * ebx_numerator / eax_denominator; }