Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753171AbcKTCPX (ORCPT ); Sat, 19 Nov 2016 21:15:23 -0500 Received: from mail-vk0-f46.google.com ([209.85.213.46]:34708 "EHLO mail-vk0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753014AbcKTCPW (ORCPT ); Sat, 19 Nov 2016 21:15:22 -0500 MIME-Version: 1.0 In-Reply-To: References: From: Andy Lutomirski Date: Sat, 19 Nov 2016 18:15:00 -0800 Message-ID: Subject: Re: What exactly do 32-bit x86 exceptions push on the stack in the CS slot? To: Brian Gerst Cc: Andy Lutomirski , tedheadster@gmail.com, Linus Torvalds , "H. Peter Anvin" , George Spelvin , "linux-kernel@vger.kernel.org" , X86 ML Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1796 Lines: 46 On Sat, Nov 19, 2016 at 6:11 PM, Brian Gerst wrote: > On Sat, Nov 19, 2016 at 8:52 PM, Andy Lutomirski wrote: >> This is a question for the old-timers here, since I can't find >> anything resembling an answer in the SDM. >> >> Suppose an exception happens (#UD in this case, but I assume it >> doesn't really matter). We're not in long mode, and the IDT is set up >> to deliver to a normal 32-bit kernel code segment. We're running in >> that very same code segment when the exception hits, so no CPL change >> occurs and the TSS doesn't particularly matter. >> >> The CPU will push EFLAGS, CS, and RIP. Here's the question: what >> happens to the high word of CS on the stack? >> >> The SDM appears to say nothing at all about this. Modern systems >> (e.g. my laptop running in 32-bit legacy mode under KVM) appear to >> zero-extend CS. But Matthew's 486DX appears to put garbage in the >> high bits (or maybe just leave whatever was already on the stack in >> place). >> >> Do any of you happen to know what's going on and when the behavior >> changed? I'd like to know just how big of a problem this is. Because >> if lots of CPUs work like Matthew's, we have lots of subtle bugs on >> them. >> >> --Andy > > This came up a while back, and we was determined that we can't assume > zero-extension in 32-bit mode because older processors only do a > 16-bit write even on a 32-bit push. So all segments have to be > treated as 16-bit values, or we have to explicitly zero-extend them. > > All 64-bit capable processors do zero-extend segments, even in 32-bit mode. This almost makes me want to change the definition of pt_regs on 32-bit rather than fixing all the entry code. > > -- > Brian Gerst -- Andy Lutomirski AMA Capital Management, LLC