Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751892AbcKTTes (ORCPT ); Sun, 20 Nov 2016 14:34:48 -0500 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:34485 "EHLO out5-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750807AbcKTTer (ORCPT ); Sun, 20 Nov 2016 14:34:47 -0500 X-ME-Sender: X-Sasl-enc: 3ogIP9V4I3EdLNwCy1tvoKTBHxyLqS8VjxOJ+JCvSjUT 1479670486 Date: Sun, 20 Nov 2016 17:34:43 -0200 From: Henrique de Moraes Holschuh To: Borislav Petkov Cc: Andy Lutomirski , Matthew Whitehead , Brian Gerst , "linux-kernel@vger.kernel.org" , X86 ML Subject: Re: [PATCH] x86/boot: Fail the boot if !M486 and CPUID is missing Message-ID: <20161120193442.GA1145@khazad-dum.debian.net> References: <70eac6639f23df8be5fe03fa1984aedd5d40077a.1479598603.git.luto@kernel.org> <20161120111917.pw3alolx4fksfwbv@pd.tnic> <20161120173244.a2odm3rupohvatiq@pd.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20161120173244.a2odm3rupohvatiq@pd.tnic> X-GPG-Fingerprint1: 4096R/0x0BD9E81139CB4807: C467 A717 507B BAFE D3C1 6092 0BD9 E811 39CB 4807 User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1055 Lines: 25 On Sun, 20 Nov 2016, Borislav Petkov wrote: > We will have set (or not) the X86_FEATURE_CPUID bit at > early_identify_cpu() time. Looking at the code, we do call sync_core() > pretty early. :-\ Hmm, watch out for the early microcode update driver for Intel processors should something get changed in the implementation, or in the behavior of sync_core(). That driver absolutely needs to issue a cpuid (with EAX = 1) before each rdmsr(MSR_IA32_UCODE_REV). And it uses sync_core() calls to do it. A CR2 access just won't do in this extremely specific case. This kind of pitfall is why I wanted to replace all use of sync_core() in arch/x86/kernel/cpu/microcode/intel.c with an explicit use of an inconditional cpuid(eax = 1)... (note: this protocol to read MSR_IA32_UCODE_REV was made an architectural requirement a while ago -- it was once considered an erratum workaround. It is documented in the "Intel 64 and IA‐32 Architectures Software Developer's Manual", Volume 3A: System Programming Guide, Part 1, section 9.11). -- Henrique Holschuh