Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755088AbcKVInJ (ORCPT ); Tue, 22 Nov 2016 03:43:09 -0500 Received: from mail-sn1nam01on0057.outbound.protection.outlook.com ([104.47.32.57]:62208 "EHLO NAM01-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752171AbcKVInH (ORCPT ); Tue, 22 Nov 2016 03:43:07 -0500 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;nxp.com; dkim=none (message not signed) header.d=none; X-IncomingTopHeaderMarker: OriginalChecksum:;UpperCasedChecksum:;SizeAsReceived:705;Count:8 From: To: CC: , , , , , Tang Yuantian , Tang Yuantian Subject: [PATCH v2] clk: qoriq: added ls1012a clock configuration Date: Tue, 22 Nov 2016 16:14:59 +0800 Message-ID: <1479802499-9083-1-git-send-email-yuantian.tang@nxp.com> X-Mailer: git-send-email 2.1.0.27.g96db324 X-IncomingHeaderCount: 8 X-EOPAttributedMessage: 0 X-Matching-Connectors: 131242768934494803;(91ab9b29-cfa4-454e-5278-08d120cd25b8);() X-Forefront-Antispam-Report: CIP:192.88.168.50;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(7916002)(2980300002)(1109001)(1110001)(339900001)(336004)(199003)(189002)(5003940100001)(50466002)(8676002)(36756003)(5660300001)(48376002)(50986999)(77096005)(104016004)(626004)(6666003)(110136003)(38730400001)(33646002)(6916009)(97736004)(305945005)(189998001)(356003)(4326007)(8666005)(87936001)(2906002)(2876002)(92566002)(7846002)(8936002)(86362001)(105606002)(575784001)(81166006)(106466001)(85426001)(68736007)(50226002)(81156014)(2351001)(86152002)(47776003)(7059030);DIR:OUT;SFP:1101;SCL:1;SRVR:MWHPR03MB2478;H:tx30smr01.am.freescale.net;FPR:;SPF:Fail;PTR:InfoDomainNonexistent;A:1;MX:1;LANG:en; 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+static const struct clockgen_muxinfo ls1012a_cmux = { + { + [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, + {}, + [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, + } +}; + static const struct clockgen_muxinfo t1040_cmux = { { [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, @@ -482,6 +490,16 @@ static const struct clockgen_chipinfo chipinfo[] = { .pll_mask = 0x03, }, { + .compat = "fsl,ls1012a-clockgen", + .cmux_groups = { + &ls1012a_cmux + }, + .cmux_to_group = { + 0, -1 + }, + .pll_mask = 0x03, + }, + { .compat = "fsl,ls1043a-clockgen", .init_periph = t2080_init_periph, .cmux_groups = { @@ -1282,6 +1300,7 @@ static void __init clockgen_init(struct device_node *np) CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init); +CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); -- 2.1.0.27.g96db324