Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932553AbcKVR0g (ORCPT ); Tue, 22 Nov 2016 12:26:36 -0500 Received: from mail-ua0-f182.google.com ([209.85.217.182]:34595 "EHLO mail-ua0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933112AbcKVR0d (ORCPT ); Tue, 22 Nov 2016 12:26:33 -0500 MIME-Version: 1.0 In-Reply-To: <20161121082721.GA22520@gmail.com> References: <20161117020610.5302-1-khuey@kylehuey.com> <20161117020610.5302-7-khuey@kylehuey.com> <20161118081444.GC15912@gmail.com> <20161121082721.GA22520@gmail.com> From: Andy Lutomirski Date: Tue, 22 Nov 2016 09:26:11 -0800 Message-ID: Subject: Re: [PATCH v12 6/7] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID To: Ingo Molnar Cc: Thomas Gleixner , Ingo Molnar , Jeff Dike , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , "open list:KERNEL SELFTEST FRAMEWORK" , Dmitry Safonov , Nadav Amit , Alexander Viro , "Rafael J. Wysocki" , Linux FS Devel , kvm list , "user-mode-linux-devel@lists.sourceforge.net" , X86 ML , "open list:USER-MODE LINUX (UML)" , Paolo Bonzini , Kyle Huey , Dave Hansen , "Robert O'Callahan" , Boris Ostrovsky , Shuah Khan , "linux-kernel@vger.kernel.org" , David Matlack , Borislav Petkov , Len Brown , Richard Weinberger , "H. Peter Anvin" , Peter Zijlstra Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1857 Lines: 46 On Nov 21, 2016 12:27 AM, "Ingo Molnar" wrote: > > > * Thomas Gleixner wrote: > > > On Fri, 18 Nov 2016, Ingo Molnar wrote: > > > * Kyle Huey wrote: > > > > + if (test_tsk_thread_flag(prev_p, TIF_NOCPUID) ^ > > > > + test_tsk_thread_flag(next_p, TIF_NOCPUID)) { > > > > + set_cpuid_faulting(test_tsk_thread_flag(next_p, TIF_NOCPUID)); > > > > + } > > > > + > > > > > > Why not cache the required MSR value in the task struct instead? > > > > > > That would allow something much more obvious and much faster, like: > > > > > > if (prev_p->thread.misc_features_val != next_p->thread.misc_features_val) > > > wrmsrl(MSR_MISC_FEATURES_ENABLES, next_p->thread.misc_features_val); > > > > > > (The TIF flag maintenance is still required to get into __switch_to_xtra().) > > > > > > It would also be easy to extend without extra overhead, should any other feature > > > bit be added to the MSR in the future. > > > > I doubt that. There are feature enable bits coming up which are not related to > > tasks. > > Any inefficiencies resulting from such features should IMHO be carried by those > features, not by per task features - but: > > > [...] So if we have switches enabling/disabling global features, then we would > > be forced to chase all threads in order to update all misc_features thread > > variables. Surely not what we want to do. > > What switches would those be? We generally don't twiddle global CPU features post > bootup - we pick a model on bootup and go with that. I don't see what problem we're trying to solve here. If we end up with a mix of global (and changeable!) features and per-task features, we can just do: wrmsrl(MSR_MISC_FEATURES_ENABLES, global_misc_features_val | next_p->thread.misc_features_val); This is *still* way faster than rdmsr.