Date: Wed, 23 Nov 2016 17:55:25 +0100
From: Borislav Petkov <bp@suse.de>
To: Tony Luck <tony.luck@gmail.com>
Cc: Henrique de Moraes Holschuh <hmh@hmh.eng.br>,
        "Luck, Tony" <tony.luck@intel.com>, Andi Kleen <andi@firstfloor.org>,
        Ashok Raj <ashok.raj@intel.com>, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] x86/mce: Include the PPIN in machine check records
 when it is available
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 <20161123132951.GA9373@khazad-dum.debian.net>
 <20161123133723.vyi7bv46h3pulldc@pd.tnic>
 <20161123140521.gkjl7vnvaneef7hv@pd.tnic>
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On Wed, Nov 23, 2016 at 08:42:40AM -0800, Tony Luck wrote:
> If the BIOS writes 10b, then PPIN is disabled and will remain so until
> the processor is reset. Bit 1 is a one way trip, it can be set by s/w,
> but not cleared again.

10b means bit 1, i.e., Enable_PPIN is set, right? Which actually
*enables* PPIN. Or am I confused again?

Otherwise, this explains the "Once set" wording - if Enable_PPIN is 1,
there's no changing until next reboot.

> All this is because of the huge stink last time Intel tried to add
> a serial number to CPUs a decade and a half ago.

It certainly rang a bell when you sent v1. :-)

> The lockout bit is so that this can be turned off in a way that you
> can be sure that it can't be turned on again.

... in order to protect ourselves from root doing wrmsr? Or why are we
doing this?

-- 
Regards/Gruss,
    Boris.

SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
--